Lines Matching +full:mac +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
49 intc: interrupt-controller@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
82 #dma-cells = <1>;
84 clock-names = "apb_pclk";
86 reset-names = "dma";
91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0>;
94 #address-cells = <0x1>;
95 #size-cells = <0x1>;
117 compatible = "altr,clk-mgr";
121 #address-cells = <1>;
122 #size-cells = <0>;
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
145 #address-cells = <1>;
146 #size-cells = <0>;
147 #clock-cells = <0>;
148 compatible = "altr,socfpga-pll-clock";
153 #clock-cells = <0>;
154 compatible = "altr,socfpga-perip-clk";
156 div-reg = <0xe0 0 9>;
161 #clock-cells = <0>;
162 compatible = "altr,socfpga-perip-clk";
164 div-reg = <0xe4 0 9>;
169 #clock-cells = <0>;
170 compatible = "altr,socfpga-perip-clk";
172 div-reg = <0xe8 0 9>;
177 #clock-cells = <0>;
178 compatible = "altr,socfpga-perip-clk";
184 #clock-cells = <0>;
185 compatible = "altr,socfpga-perip-clk";
191 #clock-cells = <0>;
192 compatible = "altr,socfpga-perip-clk";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 #clock-cells = <0>;
202 compatible = "altr,socfpga-pll-clock";
207 #clock-cells = <0>;
208 compatible = "altr,socfpga-perip-clk";
214 #clock-cells = <0>;
215 compatible = "altr,socfpga-perip-clk";
221 #clock-cells = <0>;
222 compatible = "altr,socfpga-perip-clk";
228 #clock-cells = <0>;
229 compatible = "altr,socfpga-perip-clk";
235 #clock-cells = <0>;
236 compatible = "altr,socfpga-perip-clk";
242 #clock-cells = <0>;
243 compatible = "altr,socfpga-perip-clk";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-pll-clock";
258 #clock-cells = <0>;
259 compatible = "altr,socfpga-perip-clk";
265 #clock-cells = <0>;
266 compatible = "altr,socfpga-perip-clk";
272 #clock-cells = <0>;
273 compatible = "altr,socfpga-perip-clk";
279 #clock-cells = <0>;
280 compatible = "altr,socfpga-perip-clk";
287 #clock-cells = <0>;
288 compatible = "altr,socfpga-perip-clk";
290 fixed-divider = <4>;
294 #clock-cells = <0>;
295 compatible = "altr,socfpga-perip-clk";
297 fixed-divider = <2>;
301 #clock-cells = <0>;
302 compatible = "altr,socfpga-gate-clk";
304 clk-gate = <0x60 0>;
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-perip-clk";
311 fixed-divider = <1>;
315 #clock-cells = <0>;
316 compatible = "altr,socfpga-gate-clk";
318 div-reg = <0x64 0 2>;
319 clk-gate = <0x60 1>;
323 #clock-cells = <0>;
324 compatible = "altr,socfpga-gate-clk";
326 div-reg = <0x64 2 2>;
330 #clock-cells = <0>;
331 compatible = "altr,socfpga-gate-clk";
333 div-reg = <0x64 4 3>;
334 clk-gate = <0x60 2>;
338 #clock-cells = <0>;
339 compatible = "altr,socfpga-gate-clk";
341 div-reg = <0x64 7 3>;
342 clk-gate = <0x60 3>;
346 #clock-cells = <0>;
347 compatible = "altr,socfpga-gate-clk";
349 div-reg = <0x68 0 2>;
350 clk-gate = <0x60 4>;
354 #clock-cells = <0>;
355 compatible = "altr,socfpga-gate-clk";
357 div-reg = <0x68 2 2>;
358 clk-gate = <0x60 5>;
362 #clock-cells = <0>;
363 compatible = "altr,socfpga-gate-clk";
365 div-reg = <0x6C 0 3>;
366 clk-gate = <0x60 6>;
370 #clock-cells = <0>;
371 compatible = "altr,socfpga-gate-clk";
373 clk-gate = <0x60 7>;
377 #clock-cells = <0>;
378 compatible = "altr,socfpga-gate-clk";
380 clk-gate = <0x60 8>;
384 #clock-cells = <0>;
385 compatible = "altr,socfpga-gate-clk";
387 clk-gate = <0x60 9>;
391 #clock-cells = <0>;
392 compatible = "altr,socfpga-gate-clk";
394 clk-gate = <0xa0 0>;
398 #clock-cells = <0>;
399 compatible = "altr,socfpga-gate-clk";
401 clk-gate = <0xa0 1>;
405 #clock-cells = <0>;
406 compatible = "altr,socfpga-gate-clk";
408 clk-gate = <0xa0 2>;
409 div-reg = <0xa4 0 3>;
413 #clock-cells = <0>;
414 compatible = "altr,socfpga-gate-clk";
416 clk-gate = <0xa0 3>;
417 div-reg = <0xa4 3 3>;
421 #clock-cells = <0>;
422 compatible = "altr,socfpga-gate-clk";
424 clk-gate = <0xa0 4>;
425 div-reg = <0xa4 6 3>;
429 #clock-cells = <0>;
430 compatible = "altr,socfpga-gate-clk";
432 clk-gate = <0xa0 5>;
433 div-reg = <0xa4 9 3>;
437 #clock-cells = <0>;
438 compatible = "altr,socfpga-gate-clk";
440 clk-gate = <0xa0 6>;
441 div-reg = <0xa8 0 24>;
445 #clock-cells = <0>;
446 compatible = "altr,socfpga-gate-clk";
448 clk-gate = <0xa0 7>;
452 #clock-cells = <0>;
453 compatible = "altr,socfpga-gate-clk";
455 clk-gate = <0xa0 8>;
459 #clock-cells = <0>;
460 compatible = "altr,socfpga-gate-clk";
462 clk-gate = <0xa0 8>;
463 fixed-divider = <4>;
467 #clock-cells = <0>;
468 compatible = "altr,socfpga-gate-clk";
470 clk-gate = <0xa0 9>;
474 #clock-cells = <0>;
475 compatible = "altr,socfpga-gate-clk";
477 clk-gate = <0xa0 9>;
481 #clock-cells = <0>;
482 compatible = "altr,socfpga-gate-clk";
484 clk-gate = <0xa0 10>;
485 fixed-divider = <4>;
489 #clock-cells = <0>;
490 compatible = "altr,socfpga-gate-clk";
492 clk-gate = <0xa0 11>;
496 #clock-cells = <0>;
497 compatible = "altr,socfpga-gate-clk";
499 clk-gate = <0xd8 0>;
503 #clock-cells = <0>;
504 compatible = "altr,socfpga-gate-clk";
506 clk-gate = <0xd8 1>;
510 #clock-cells = <0>;
511 compatible = "altr,socfpga-gate-clk";
513 clk-gate = <0xd8 2>;
517 #clock-cells = <0>;
518 compatible = "altr,socfpga-gate-clk";
520 clk-gate = <0xd8 3>;
527 compatible = "altr,socfpga-lwhps2fpga-bridge";
535 compatible = "altr,socfpga-hps2fpga-bridge";
542 fpga_bridge2: fpga-bridge@ff600000 {
543 compatible = "altr,socfpga-fpga2hps-bridge";
550 fpga_bridge3: fpga-bridge@ffc25080 {
551 compatible = "altr,socfpga-fpga2sdram-bridge";
557 compatible = "altr,socfpga-fpga-mgr";
563 socfpga_axi_setup: stmmac-axi-config {
570 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
571 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
574 interrupt-names = "macirq";
575 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
577 clock-names = "stmmaceth";
579 reset-names = "stmmaceth";
580 snps,multicast-filter-bins = <256>;
581 snps,perfect-filter-entries = <128>;
582 tx-fifo-depth = <4096>;
583 rx-fifo-depth = <4096>;
584 snps,axi-config = <&socfpga_axi_setup>;
589 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
590 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
593 interrupt-names = "macirq";
594 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
596 clock-names = "stmmaceth";
598 reset-names = "stmmaceth";
599 snps,multicast-filter-bins = <256>;
600 snps,perfect-filter-entries = <128>;
601 tx-fifo-depth = <4096>;
602 rx-fifo-depth = <4096>;
603 snps,axi-config = <&socfpga_axi_setup>;
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "snps,dw-apb-gpio";
616 porta: gpio-controller@0 {
617 compatible = "snps,dw-apb-gpio-port";
618 gpio-controller;
619 #gpio-cells = <2>;
620 snps,nr-gpios = <29>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "snps,dw-apb-gpio";
637 portb: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <29>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,dw-apb-gpio";
658 portc: gpio-controller@0 {
659 compatible = "snps,dw-apb-gpio-port";
660 gpio-controller;
661 #gpio-cells = <2>;
662 snps,nr-gpios = <27>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
671 #address-cells = <1>;
672 #size-cells = <0>;
673 compatible = "snps,designware-i2c";
682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "snps,designware-i2c";
693 #address-cells = <1>;
694 #size-cells = <0>;
695 compatible = "snps,designware-i2c";
704 #address-cells = <1>;
705 #size-cells = <0>;
706 compatible = "snps,designware-i2c";
715 compatible = "altr,socfpga-ecc-manager";
716 #address-cells = <1>;
717 #size-cells = <1>;
720 l2-ecc@ffd08140 {
721 compatible = "altr,socfpga-l2-ecc";
726 ocram-ecc@ffd08144 {
727 compatible = "altr,socfpga-ocram-ecc";
734 L2: cache-controller@fffef000 {
735 compatible = "arm,pl310-cache";
738 cache-unified;
739 cache-level = <2>;
740 arm,tag-latency = <1 1 1>;
741 arm,data-latency = <2 1 1>;
742 prefetch-data = <1>;
743 prefetch-instr = <1>;
744 arm,shared-override;
745 arm,double-linefill = <1>;
746 arm,double-linefill-incr = <0>;
747 arm,double-linefill-wrap = <1>;
748 arm,prefetch-drop = <0>;
749 arm,prefetch-offset = <7>;
758 compatible = "altr,socfpga-dw-mshc";
761 fifo-depth = <0x400>;
762 #address-cells = <1>;
763 #size-cells = <0>;
765 clock-names = "biu", "ciu";
767 altr,sysmgr-syscon = <&sysmgr 0x108 3>;
771 nand0: nand-controller@ff900000 {
772 #address-cells = <0x1>;
773 #size-cells = <0x0>;
774 compatible = "altr,socfpga-denali-nand";
777 reg-names = "nand_data", "denali_reg";
780 clock-names = "nand", "nand_x", "ecc";
786 compatible = "mmio-sram";
791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
792 #address-cells = <1>;
793 #size-cells = <0>;
797 cdns,fifo-depth = <128>;
798 cdns,fifo-width = <4>;
799 cdns,trigger-address = <0x00000000>;
806 #reset-cells = <1>;
807 compatible = "altr,rst-mgr";
809 altr,modrst-offset = <0x10>;
812 scu: snoop-control-unit@fffec000 {
813 compatible = "arm,cortex-a9-scu";
818 compatible = "altr,sdr-ctl", "syscon";
824 compatible = "altr,sdram-edac";
825 altr,sdr-syscon = <&sdr>;
830 compatible = "snps,dw-apb-ssi";
831 #address-cells = <1>;
832 #size-cells = <0>;
835 num-cs = <4>;
838 reset-names = "spi";
843 compatible = "snps,dw-apb-ssi";
844 #address-cells = <1>;
845 #size-cells = <0>;
848 num-cs = <4>;
851 reset-names = "spi";
856 compatible = "altr,sys-mgr", "syscon";
862 compatible = "arm,cortex-a9-twd-timer";
869 compatible = "snps,dw-apb-timer";
873 clock-names = "timer";
875 reset-names = "timer";
879 compatible = "snps,dw-apb-timer";
883 clock-names = "timer";
885 reset-names = "timer";
889 compatible = "snps,dw-apb-timer";
893 clock-names = "timer";
895 reset-names = "timer";
899 compatible = "snps,dw-apb-timer";
903 clock-names = "timer";
905 reset-names = "timer";
909 compatible = "snps,dw-apb-uart";
912 reg-shift = <2>;
913 reg-io-width = <4>;
917 dma-names = "tx", "rx";
922 compatible = "snps,dw-apb-uart";
925 reg-shift = <2>;
926 reg-io-width = <4>;
930 dma-names = "tx", "rx";
935 #phy-cells = <0>;
936 compatible = "usb-nop-xceiv";
945 clock-names = "otg";
947 reset-names = "dwc2";
949 phy-names = "usb2-phy";
958 clock-names = "otg";
960 reset-names = "dwc2";
962 phy-names = "usb2-phy";
967 compatible = "snps,dw-wdt";
976 compatible = "snps,dw-wdt";