| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | realtek,usb2phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
33 XHCI controller#0 -- usb2phy -- phy#0
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| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
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| H A D | driver.rst | 26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
10 related domain pad driving selection, if the related domain pad
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
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| H A D | mediatek,mt8183-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
17 const: mediatek,mt8183-pinctrl
23 reg-names:
25 - const: iocfg0
26 - const: iocfg1
27 - const: iocfg2
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| H A D | mediatek,mt8365-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
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| H A D | realtek,rtd1315e-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1315E is a high-definition media processor SoC. The
20 const: realtek,rtd1315e-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
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| H A D | realtek,rtd1619b-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1619b-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1619B is a high-definition media processor SoC. The
20 const: realtek,rtd1619b-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
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| H A D | realtek,rtd1319d-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1319D is a high-definition media processor SoC. The
20 const: realtek,rtd1319d-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
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| H A D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
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| /linux/include/media/ |
| H A D | cec-pin.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cec-pin.h - low-level CEC pin control
15 * struct cec_pin_ops - low-level CEC pin operations
19 * @high: stop driving the CEC pin. The pull-up will drive the pin
20 * high, unless someone else is driving the pin low.
30 * @received: optional. High-level CEC message callback. Allows the driver
47 /* High-level CEC message callback */
52 * cec_pin_changed() - update pin state from interrupt
63 * cec_pin_allocate_adapter() - allocate a pin-based cec adapter
65 * @pin_ops: low-level pin operations
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| /linux/Documentation/devicetree/bindings/leds/backlight/ |
| H A D | richtek,rt4831-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 For the LCD backlight, it can provide four channel WLED driving capability.
17 Each channel driving current is up to 30mA
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led | 9 just be turned on for non-zero brightness settings.
23 Documentation/leds/leds-class-multicolor.rst.
30 Writing non-zero to this file while trigger is active changes the
40 Maximum brightness level for this LED, default is 255 (LED_FULL).
49 Last hardware set brightness level for this LED. Some LEDs
57 Reading this file will return the last brightness level set
73 their documentation see `sysfs-class-led-trigger-*`.
82 it is useful when driving a LED which is intended to indicate
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | cdns,gpio.txt | 4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
17 - interrupts: interrupt specifier for the controllers interrupt.
18 - interrupt-controller: marks the device as an interrupt controller. When
19 defined, interrupts, interrupt-parent and #interrupt-cells
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| H A D | nxp,pcf8575.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
15 combines the direction and output level into a single bit per line, which
17 line is configured (a) as output and driving the signal low/high, or (b) as
25 - maxim,max7328
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| /linux/include/linux/pinctrl/ |
| H A D | pinconf-generic.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 * enum pin_config_param - possible pin configuration parameters
28 * bus to change the value by driving the bus high or low and switching to
31 * transition from say pull-up to pull-down implies that you disable
32 * pull-up in the process, this setting disables all biasing.
34 * mode, also know as "third-state" (tristate) or "high-Z" or "floating".
40 * impedance to GROUND). If the argument is != 0 pull-down is enabled,
52 * impedance to VDD). If the argument is != 0 pull-up is enabled,
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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| /linux/Documentation/arch/arm/pxa/ |
| H A D | mfp.rst | 7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
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| /linux/Documentation/timers/ |
| H A D | timers-howto.rst | 2 delays - Information on the various kernel delay / sleep mechanisms
14 ----------------
30 udelay is the generally preferred API; ndelay-level
31 precision may not actually exist on many non-PC devices.
38 NON-ATOMIC CONTEXT:
45 -- Backed by busy-wait loop:
49 -- Backed by hrtimers:
53 -- Backed by jiffies / legacy_timers
59 driving each of these calls varies, thus there are
66 - Why not usleep?
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| /linux/include/linux/mfd/ |
| H A D | idt8a340_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
69 * Unused when FOD4 is driving Q8 divider (normal operation).
77 * Unused when FOD4 is driving Q8 divider (normal operation).
86 * Unused when FOD7 is driving Q11 divider (normal operation).
94 * Unused when FOD7 is driving Q11 divider (normal operation).
230 /* Signed 42-bit FFO in units of 2^(-53) */
241 /* Signed 42-bit FFO in units of 2^(-53) */
380 /* Enable TOD counter, output channel sync and even-PPS mode */
392 /* 8-bit subns, 32-bit ns, 48-bit seconds */
409 /* 8-bit subns, 32-bit ns, 48-bit seconds */
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| /linux/drivers/irqchip/ |
| H A D | irq-renesas-irqc.c | 1 // SPDX-License-Identifier: GPL-2.0
26 /* SYS-CPU vs. RT-CPU */
28 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
29 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
30 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
58 return data->domain->host_data; in irq_data_to_priv()
63 dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq); in irqc_dbg()
81 irqc_dbg(&p->irq[hw_irq], "sense"); in irqc_irq_set_type()
84 return -EINVAL; in irqc_irq_set_type()
86 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); in irqc_irq_set_type()
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| /linux/drivers/hid/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 most commonly used to refer to the USB-HID specification, but other
27 removed from the HID bus by the transport-layer drivers, such as
37 bool "Battery level reporting for HID devices"
58 to work on raw hid events when they want to, and avoid using transport-specific
64 tristate "User-space I/O driver support for HID subsystem"
67 Say Y here if you want to provide HID I/O Drivers from user-space.
68 This allows to write I/O drivers in user-space and feed the data from
71 user-space device.
73 This driver cannot be used to parse HID-reports in user-space and write
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| /linux/include/linux/i3c/ |
| H A D | master.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
39 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
62 * struct i2c_dev_boardinfo - I2C device board information
68 * This structure is used to attach board-level information to an I2C device.
78 * struct i2c_dev_desc - I2C device descriptor
87 * using &struct_i3c_master_controller->ops->attach_i2c_dev().
101 * struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot
108 * An IBI slot is an object pre-allocated by the controller and used when an
115 * simple kmalloc-based allocation, the generic IBI slot pool can be used.
125 * struct i3c_device_ibi_info - IBI information attached to a specific device
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
39 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
43 * sideband. VLV has one such PHY for driving ports B and C, and CHV
44 * adds another PHY for driving port D. Each PHY responds to specific
45 * IOSF-SB port.
49 * logic. CH0 common lane also contains the IOSF-SB logic for the
59 * each spline is made up of one Physical Access Coding Sub-Layer
103 * ---------------------------------
106 * |---------------|---------------| Display PHY
108 * |-------|-------|-------|-------|
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