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/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
33 XHCI controller#0 -- usb2phy -- phy#0
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/linux/Documentation/driver-api/gpio/
H A Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsprd,pinctrl.txt8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
10 related domain pad driving selection, if the related domain pad
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
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H A Dmediatek,mt8365-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
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H A Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
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/linux/include/media/
H A Dcec-pin.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cec-pin.h - low-level CEC pin control
15 * struct cec_pin_ops - low-level CEC pin operations
19 * @high: stop driving the CEC pin. The pull-up will drive the pin
20 * high, unless someone else is driving the pin low.
30 * @received: optional. High-level CEC message callback. Allows the driver
47 /* High-level CEC message callback */
52 * cec_pin_changed() - update pin state from interrupt
63 * cec_pin_allocate_adapter() - allocate a pin-based cec adapter
65 * @pin_ops: low-level pin operations
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/linux/Documentation/devicetree/bindings/leds/backlight/
H A Drichtek,rt4831-backlight.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 For the LCD backlight, it can provide four channel WLED driving capability.
17 Each channel driving current is up to 30mA
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-led9 just be turned on for non-zero brightness settings.
23 Documentation/leds/leds-class-multicolor.rst.
30 Writing non-zero to this file while trigger is active changes the
40 Maximum brightness level for this LED, default is 255 (LED_FULL).
49 Last hardware set brightness level for this LED. Some LEDs
57 Reading this file will return the last brightness level set
73 their documentation see `sysfs-class-led-trigger-*`.
88 it is useful when driving a LED which is intended to indicate
/linux/Documentation/devicetree/bindings/gpio/
H A Dnxp,pcf8575.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
15 combines the direction and output level into a single bit per line, which
17 line is configured (a) as output and driving the signal low/high, or (b) as
25 - maxim,max7328
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/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
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/linux/include/linux/mfd/
H A Didt8a340_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
69 * Unused when FOD4 is driving Q8 divider (normal operation).
77 * Unused when FOD4 is driving Q8 divider (normal operation).
86 * Unused when FOD7 is driving Q11 divider (normal operation).
94 * Unused when FOD7 is driving Q11 divider (normal operation).
230 /* Signed 42-bit FFO in units of 2^(-53) */
241 /* Signed 42-bit FFO in units of 2^(-53) */
380 /* Enable TOD counter, output channel sync and even-PPS mode */
392 /* 8-bit subns, 32-bit ns, 48-bit seconds */
409 /* 8-bit subns, 32-bit ns, 48-bit seconds */
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/linux/drivers/irqchip/
H A Dirq-renesas-irqc.c1 // SPDX-License-Identifier: GPL-2.0
26 /* SYS-CPU vs. RT-CPU */
28 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
29 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
30 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
58 return data->domain->host_data; in irq_data_to_priv()
63 dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq); in irqc_dbg()
81 irqc_dbg(&p->irq[hw_irq], "sense"); in irqc_irq_set_type()
84 return -EINVAL; in irqc_irq_set_type()
86 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); in irqc_irq_set_type()
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/linux/drivers/hid/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 most commonly used to refer to the USB-HID specification, but other
27 removed from the HID bus by the transport-layer drivers, such as
37 bool "Battery level reporting for HID devices"
58 to work on raw hid events when they want to, and avoid using transport-specific
64 tristate "User-space I/O driver support for HID subsystem"
67 Say Y here if you want to provide HID I/O Drivers from user-space.
68 This allows to write I/O drivers in user-space and feed the data from
71 user-space device.
73 This driver cannot be used to parse HID-reports in user-space and write
[all …]
/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "sc7180-firmware-tfa.dtsi"
22 thermal-zones {
23 charger_thermal: charger-thermal {
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/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux/drivers/i2c/busses/
H A Di2c-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * ----------------------------------------------------------------------------
12 * ----------------------------------------------------------------------------
32 /* ----- global defines ----------------------------------------------- */
102 /* read SCL GPIO level */
104 /* read SDA GPIO level */
146 writew_relaxed(val, i2c_dev->base + reg); in davinci_i2c_write_reg()
151 return readw_relaxed(i2c_dev->base + reg); in davinci_i2c_read_reg()
175 u32 input_clock = clk_get_rate(dev->clk); in i2c_davinci_calc_clk_dividers()
180 * input clk --> PSC Div -----------> ICCL/H Div --> output clock in i2c_davinci_calc_clk_dividers()
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/linux/drivers/bus/
H A Dqcom-ssc-block-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
68 ret = clk_prepare_enable(data->xo_clk); in qcom_ssc_block_bus_init()
74 ret = clk_prepare_enable(data->aggre2_clk); in qcom_ssc_block_bus_init()
80 ret = clk_prepare_enable(data->gcc_im_sleep_clk); in qcom_ssc_block_bus_init()
87 * We need to intervene here because the HW logic driving these signals cannot handle in qcom_ssc_block_bus_init()
90 reg32_clear_bits(data->reg_mpm_sscaon_config0, in qcom_ssc_block_bus_init()
93 reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31)); in qcom_ssc_block_bus_init()
95 ret = clk_prepare_enable(data->aggre2_north_clk); in qcom_ssc_block_bus_init()
101 ret = reset_control_deassert(data->ssc_reset); in qcom_ssc_block_bus_init()
107 ret = reset_control_deassert(data->ssc_bcr); in qcom_ssc_block_bus_init()
[all …]
/linux/drivers/gpio/
H A Dgpio-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
61 #define EDGLEVEL 0x24 /* Edge/level Select Register */
71 return ioread32(p->base + offs); in gpio_rcar_read()
77 iowrite32(value, p->base + offs); in gpio_rcar_write()
122 * "Setting Edge-Sensitive Interrupt Input Mode" and in gpio_rcar_config_interrupt_input_mode()
123 * "Setting Level-Sensitive Interrupt Input Mode" in gpio_rcar_config_interrupt_input_mode()
126 raw_spin_lock_irqsave(&p->lock, flags); in gpio_rcar_config_interrupt_input_mode()
131 /* Configure edge or level trigger in EDGLEVEL */ in gpio_rcar_config_interrupt_input_mode()
135 if (p->info.has_both_edge_trigger) in gpio_rcar_config_interrupt_input_mode()
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
[all …]
/linux/drivers/power/reset/
H A Dat91-reset.c6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
37 #define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */
47 * enum reset_type - reset types
48 * @RESET_TYPE_GENERAL: first power-up reset
69 * struct at91_reset - AT91 reset specific data structure
97 * struct at91_reset_data - AT91 reset data
112 * reset register it can be left driving the data bus and
140 : "r" (reset->ramc_base[0]), in at91_reset()
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/linux/drivers/usb/gadget/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
25 you can't connect a "to-the-host" connector to a peripheral.
28 you need a low level bus controller driver, and some software
44 For more information, see <http://www.linux-usb.org/gadget> and
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/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
60 .. code-block:: c
97 See ``arch/arm/mach-ux500/Kconfig`` for an example.
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