1 // SPDX-License-Identifier: GPL-2.0
26 				/* SYS-CPU vs. RT-CPU */
28 #define MONITOR		0x104	/* IRQn Signal Level Monitor Register */
29 #define HLVL_STS	0x108	/* IRQn High Level Detect Status Register */
30 #define LLVL_STS	0x10c	/* IRQn Low Level Detect Status Register */
58 	return data->domain->host_data;  in irq_data_to_priv()
63 	dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq);  in irqc_dbg()
81 	irqc_dbg(&p->irq[hw_irq], "sense");  in irqc_irq_set_type()
84 		return -EINVAL;  in irqc_irq_set_type()
86 	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));  in irqc_irq_set_type()
89 	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));  in irqc_irq_set_type()
98 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);  in irqc_irq_set_wake()
100 		atomic_inc(&p->wakeup_path);  in irqc_irq_set_wake()
102 		atomic_dec(&p->wakeup_path);  in irqc_irq_set_wake()
110 	struct irqc_priv *p = i->p;  in irqc_irq_handler()
111 	u32 bit = BIT(i->hw_irq);  in irqc_irq_handler()
115 	if (ioread32(p->iomem + DETECT_STATUS) & bit) {  in irqc_irq_handler()
116 		iowrite32(bit, p->iomem + DETECT_STATUS);  in irqc_irq_handler()
118 		generic_handle_domain_irq(p->irq_domain, i->hw_irq);  in irqc_irq_handler()
126 	struct device *dev = &pdev->dev;  in irqc_probe()
134 		return -ENOMEM;  in irqc_probe()
136 	p->dev = dev;  in irqc_probe()
145 		if (ret == -ENXIO)  in irqc_probe()
150 		p->irq[k].p = p;  in irqc_probe()
151 		p->irq[k].hw_irq = k;  in irqc_probe()
152 		p->irq[k].requested_irq = ret;  in irqc_probe()
155 	p->number_of_irqs = k;  in irqc_probe()
156 	if (p->number_of_irqs < 1) {  in irqc_probe()
158 		ret = -EINVAL;  in irqc_probe()
163 	p->iomem = devm_platform_ioremap_resource(pdev, 0);  in irqc_probe()
164 	if (IS_ERR(p->iomem)) {  in irqc_probe()
165 		ret = PTR_ERR(p->iomem);  in irqc_probe()
169 	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */  in irqc_probe()
171 	p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs,  in irqc_probe()
173 	if (!p->irq_domain) {  in irqc_probe()
174 		ret = -ENXIO;  in irqc_probe()
179 	ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,  in irqc_probe()
187 	p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);  in irqc_probe()
188 	p->gc->reg_base = p->cpu_int_base;  in irqc_probe()
189 	p->gc->chip_types[0].regs.enable = IRQC_EN_SET;  in irqc_probe()
190 	p->gc->chip_types[0].regs.disable = IRQC_EN_STS;  in irqc_probe()
191 	p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;  in irqc_probe()
192 	p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;  in irqc_probe()
193 	p->gc->chip_types[0].chip.irq_set_type	= irqc_irq_set_type;  in irqc_probe()
194 	p->gc->chip_types[0].chip.irq_set_wake	= irqc_irq_set_wake;  in irqc_probe()
195 	p->gc->chip_types[0].chip.flags	= IRQCHIP_MASK_ON_SUSPEND;  in irqc_probe()
197 	irq_domain_set_pm_device(p->irq_domain, dev);  in irqc_probe()
200 	for (k = 0; k < p->number_of_irqs; k++) {  in irqc_probe()
201 		if (devm_request_irq(dev, p->irq[k].requested_irq,  in irqc_probe()
202 				     irqc_irq_handler, 0, name, &p->irq[k])) {  in irqc_probe()
204 			ret = -ENOENT;  in irqc_probe()
209 	dev_info(dev, "driving %d irqs\n", p->number_of_irqs);  in irqc_probe()
214 	irq_domain_remove(p->irq_domain);  in irqc_probe()
225 	irq_domain_remove(p->irq_domain);  in irqc_remove()
226 	pm_runtime_put(&pdev->dev);  in irqc_remove()
227 	pm_runtime_disable(&pdev->dev);  in irqc_remove()
234 	if (atomic_read(&p->wakeup_path))  in irqc_suspend()