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/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
46 * @da: device address
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
[all …]
/linux/drivers/soc/sunxi/
H A Dsunxi_sram.c2 * Allwinner SoCs SRAM Controller Driver
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
61 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
75 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
86 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
90 .compatible = "allwinner,sun4i-a10-sram-c1",
94 .compatible = "allwinner,sun4i-a10-sram-d",
98 .compatible = "allwinner,sun50i-a64-sram-c",
104 static struct device *sram_dev;
117 seq_puts(s, "Allwinner sunXi SRAM\n"); in sunxi_sram_show()
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/linux/drivers/crypto/ccree/
H A Dcc_sram_mgr.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
8 * cc_sram_mgr_init() - Initializes SRAM pool.
9 * The pool starts right at the beginning of SRAM.
12 * @drvdata: Associated device driver context
20 struct device *dev = drvdata_to_dev(drvdata); in cc_sram_mgr_init()
22 if (drvdata->hw_rev < CC_HW_REV_712) { in cc_sram_mgr_init()
26 dev_err(dev, "Invalid SRAM offset 0x%x\n", start); in cc_sram_mgr_init()
27 return -EINVAL; in cc_sram_mgr_init()
31 drvdata->sram_free_offset = start; in cc_sram_mgr_init()
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H A Dcc_sram_mgr.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
13 #define NULL_SRAM_ADDR ((u32)-1)
16 * cc_sram_mgr_init() - Initializes SRAM pool.
17 * The first X bytes of SRAM are reserved for ROM usage, hence, pool
20 * @drvdata: Associated device driver context
28 * cc_sram_alloc() - Allocate buffer from SRAM pool.
30 * @drvdata: Associated device driver context
34 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
39 * cc_set_sram_desc() - Create const descriptors sequence to
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/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
29 the system SRAM) for different peripheral. It can access external RAMs but
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
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/linux/drivers/memory/
H A Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
99 functions of the driver includes re-configuring AC timing
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/linux/arch/arm/mach-omap2/
H A Dsram.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * OMAP SRAM detection and management
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
29 #include "sram.h"
48 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
57 * Memory allocator for SRAM: calculates the new ceiling address
61 * to an 8-byte boundary.
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
70 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
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/linux/Documentation/devicetree/bindings/net/
H A Dallwinner,sun4i-a10-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun4i-a10-emac
29 allwinner,sram:
30 description: Phandle to the device SRAM
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
25 host processor (Arm CorePac) to perform the device management of the remote
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/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
[all …]
/linux/arch/arm/mach-rockchip/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 struct device *dev = get_cpu_device(cpu); in rockchip_get_core_reset()
55 /* The cpu device is only available after the initial core bringup */ in rockchip_get_core_reset()
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
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/linux/Documentation/devicetree/bindings/mtd/
H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
29 - interrupts : interrupt used by the controller
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/linux/drivers/net/wireless/intel/iwlegacy/
H A Dprph.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
105 * in special SRAM that does not power down when the embedded control
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
109 * internally loads the short bootstrap program from the special SRAM into the
110 * embedded processor's instruction SRAM, and starts the processor so it runs
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
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/linux/Documentation/devicetree/bindings/media/
H A Dallwinner,sun4i-a10-video-engine.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
19 - allwinner,sun8i-a33-video-engine
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]
H A Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 SRAM or NOR) depending on the specific configuration.
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
27 - arm,pl354
29 - compatible
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/linux/drivers/misc/
H A Dsram-exec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SRAM protect-exec region helper functions
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/device.h>
12 #include <linux/sram.h>
17 #include "sram.h"
22 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
25 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec()
26 unsigned long end = base + block->size; in sram_check_protect_exec()
29 dev_err(sram->dev, in sram_check_protect_exec()
[all …]
H A Dsram.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Generic on-chip SRAM allocation driver
19 #include <soc/at91/atmel-secumod.h>
21 #include "sram.h"
33 mutex_lock(&part->lock); in sram_read()
34 memcpy_fromio(buf, part->base + pos, count); in sram_read()
35 mutex_unlock(&part->lock); in sram_read()
48 mutex_lock(&part->lock); in sram_write()
49 memcpy_toio(part->base + pos, buf, count); in sram_write()
50 mutex_unlock(&part->lock); in sram_write()
[all …]
/linux/drivers/fsi/
H A Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/device.h>
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
82 /* Amount of SRAM required */
89 struct device *dev;
111 void __iomem *sram; member
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
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/linux/drivers/rtc/
H A Drtc-gamecube.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver is for the MX23L4005, more specifically its real-time clock and
6 * SRAM storage. The value returned by the RTC counter must be added with the
7 * offset stored in a bias register in SRAM (on the GameCube and Wii) or in
10 * SRAM like for the other two consoles.
12 * This device sits on a bus named EXI (which is similar to SPI), channel 0,
13 * device 1. This driver assumes no other user of the EXI bus, which is
18 * - https://wiiubrew.org/wiki/Hardware/RTC
19 * - https://wiibrew.org/wiki/MX23L4005
21 * Copyright (C) 2018 rw-r-r-0644
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/linux/arch/powerpc/boot/dts/
H A Dmotionpro.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Motion-PRO board Device Tree Source
11 &gpt0 { fsl,has-wdt; };
12 &gpt6 { // Motion-PRO status LED
13 compatible = "promess,motionpro-led";
14 label = "motionpro-statusled";
15 blink-delay = <100>; // 100 msec
17 &gpt7 { // Motion-PRO ready LED
18 compatible = "promess,motionpro-led";
19 label = "motionpro-readyled";
[all …]
/linux/drivers/atm/
H A Dnicstar.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Header file for the nicstar device driver.
29 controlled by the device driver. Must
44 have 32K x 32bit SRAM, in which case
48 128K x 32bit SRAM will limit the maximum
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
99 * BUG_SM and BUG_LG are both used by the driver and the device.
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
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