Lines Matching +full:device +full:- +full:sram
1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
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11 This document describes the STM32 DMA-MDMA chaining feature. But before going
29 the system SRAM) for different peripheral. It can access external RAMs but
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
60 case, the linked-list loops on to create a circular MDMA transfer.
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110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
113 bad with DDR, while they are optimal with SRAM. Hence the SRAM buffer used
119 dma[1:2]-tcf[0:7]
120 .----------------.
123 |------------| | / \ | |------------|
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
128 STM32 DMA-MDMA chaining uses (struct dma_slave_config).peripheral_config to
137 Device Tree updates for STM32 DMA-MDMA chaining support
138 -------------------------------------------------------
140 **1. Allocate a SRAM buffer**
142 SRAM device tree node is defined in SoC device tree. You can refer to it in
143 your board device tree to define your SRAM pool.
146 &sram {
147 my_foo_device_dma_pool: dma-sram@0 {
152 Be careful of the start index, in case there are other SRAM consumers.
155 SRAM.
156 If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
160 Don't forget to refer to your SRAM pool in your device node. You need to
169 Then get this SRAM pool in your foo driver and allocate your SRAM buffer.
173 You need to define an extra channel in your device tree node, in addition to
210 Driver updates for STM32 DMA-MDMA chaining support in foo driver
211 ----------------------------------------------------------------
217 STM32 DMA transfer (where memory address targets now the SRAM buffer instead
221 The new sg_list items must fit SRAM period length. Here is an example for
254 s->dma_address = sram_buf;
260 s->dma_address += sram_period;
276 len -= bytes;
295 SRAM buffer, and set (struct dma_slave_config).peripheral_size != 0.
305 configure STM32 MDMA channel. Take care of DMA addresses, the device address
306 (depending on the transfer direction) must point on your SRAM buffer, and
320 config.dst_addr = sram_dma_buf; // SRAM buffer
327 mdma_conf.src_addr = sram_dma_buf; // SRAM buffer
329 mdma_conf.peripheral_size = dma_conf.peripheral_size; // <- dma_conf
330 mdma_conf.peripheral_config = dma_config.peripheral_config; // <- dma_conf
338 dmaengine_prep_slave_sg()) with the new sg_list using SRAM buffer, or to
340 dmaengine_prep_dma_cyclic()) with the new SRAM buffer.
351 Use the new sg_list using SRAM buffer (in case of dmaengine_prep_slave_sg())
353 case of DMA_DEV_TO_MEM) or the SRAM buffer (in case of DMA_MEM_TO_DEV), the
378 cyclic Double-Buffer mode so it won't be disabled by HW, you need to terminate
382 **STM32 DMA-MDMA chaining DMA_MEM_TO_DEV special case**
384 STM32 DMA-MDMA chaining in DMA_MEM_TO_DEV is a special case. Indeed, the
385 STM32 MDMA feeds the SRAM buffer with the DDR data, and the STM32 DMA reads
386 data from SRAM buffer. So some data (the first period) have to be copied in
387 SRAM buffer when the STM32 DMA starts to read.
391 by the STM32 DMA could be "wrong". The proper way is to prepare the first SRAM
395 Due to this complexity, rather use the STM32 DMA-MDMA chaining for
400 ---------
408 .. _STM32MP1: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
409 …24: https://www.st.com/resource/en/application_note/an5224-stm32-dmamux-the-dma-request-router-stm…
410 …st.com/resource/en/application_note/dm00046011-using-the-stm32f2-stm32f4-and-stm32f7-series-dma-co…
411 …s://www.st.com/resource/en/application_note/an5001-stm32cube-expansion-package-for-stm32h7-series-…
415 - Amelie Delaunay <amelie.delaunay@foss.st.com>