Lines Matching +full:device +full:- +full:sram

1 // SPDX-License-Identifier: GPL-2.0-only
4  * OMAP SRAM detection and management
9  * Copyright (C) 2009-2012 Texas Instruments
10  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
29 #include "sram.h"
48 #define ROUND_DOWN(value, boundary)	((value) & (~((boundary) - 1)))
57  * Memory allocator for SRAM: calculates the new ceiling address
61  * to an 8-byte boundary.
67 	available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);  in omap_sram_push_address()
70 		pr_err("Not enough space in SRAM\n");  in omap_sram_push_address()
74 	new_ceil -= size;  in omap_sram_push_address()
83 	void *sram;  in omap_sram_push()  local
88 	sram = omap_sram_push_address(size);  in omap_sram_push()
89 	if (!sram)  in omap_sram_push()
92 	base = (unsigned long)sram & PAGE_MASK;  in omap_sram_push()
97 	dst = fncpy(sram, funcp, size);  in omap_sram_push()
105  * The SRAM context is lost during off-idle and stack
115  * SRAM varies.  The default accessible size for all device types is 2k. A GP
116  * device allows ARM11 but not other initiators for full size. This
124 			writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */  in is_sram_locked()
125 			writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */  in is_sram_locked()
126 			writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */  in is_sram_locked()
129 			writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */  in is_sram_locked()
130 			writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */  in is_sram_locked()
131 			writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */  in is_sram_locked()
141  * The amount of SRAM depends on the core type.
142  * Note that we cannot try to test for SRAM here because writes
143  * to secure SRAM will hang the system. Also the SRAM is not
178  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
188 		 * SRAM must be marked as non-cached on OMAP3 since the  in omap2_map_sram()
189 		 * CORE DPLL M2 divider change code (in SRAM) runs with the  in omap2_map_sram()
203 		pr_err("SRAM: Could not map\n");  in omap2_map_sram()
211 	 * beginning of SRAM for jumping to flash for reboot to work...  in omap2_map_sram()
214 		  omap_sram_size - omap_sram_skip);  in omap2_map_sram()