xref: /linux/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1f4d7e6f6STinghan Shen# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2f4d7e6f6STinghan Shen%YAML 1.2
3f4d7e6f6STinghan Shen---
4f4d7e6f6STinghan Shen$id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml#
5f4d7e6f6STinghan Shen$schema: http://devicetree.org/meta-schemas/core.yaml#
6f4d7e6f6STinghan Shen
784e85359SKrzysztof Kozlowskititle: Mediatek SCP
8f4d7e6f6STinghan Shen
9f4d7e6f6STinghan Shenmaintainers:
10f4d7e6f6STinghan Shen  - Tinghan Shen <tinghan.shen@mediatek.com>
11f4d7e6f6STinghan Shen
12f4d7e6f6STinghan Shendescription:
13f4d7e6f6STinghan Shen  This binding provides support for ARM Cortex M4 Co-processor found on some
14f4d7e6f6STinghan Shen  Mediatek SoCs.
15f4d7e6f6STinghan Shen
16f4d7e6f6STinghan Shenproperties:
17f4d7e6f6STinghan Shen  compatible:
18f4d7e6f6STinghan Shen    enum:
19f4d7e6f6STinghan Shen      - mediatek,mt8183-scp
2022335385SAllen-KH Cheng      - mediatek,mt8186-scp
2116557244STinghan Shen      - mediatek,mt8188-scp
2291e0d560SOlivia Wen      - mediatek,mt8188-scp-dual
23f4d7e6f6STinghan Shen      - mediatek,mt8192-scp
24f4d7e6f6STinghan Shen      - mediatek,mt8195-scp
256b55b1e2STinghan Shen      - mediatek,mt8195-scp-dual
26f4d7e6f6STinghan Shen
27f4d7e6f6STinghan Shen  reg:
28f4d7e6f6STinghan Shen    description:
296bbe1065SNícolas F. R. A. Prado      Should contain the address ranges for memory regions SRAM, CFG, and,
306bbe1065SNícolas F. R. A. Prado      on some platforms, L1TCM.
316bbe1065SNícolas F. R. A. Prado    minItems: 2
32f4d7e6f6STinghan Shen    maxItems: 3
33f4d7e6f6STinghan Shen
34f4d7e6f6STinghan Shen  reg-names:
356bbe1065SNícolas F. R. A. Prado    minItems: 2
366b55b1e2STinghan Shen    maxItems: 3
37f4d7e6f6STinghan Shen
38f4d7e6f6STinghan Shen  clocks:
39f4d7e6f6STinghan Shen    description:
40f4d7e6f6STinghan Shen      Clock for co-processor (see ../clock/clock-bindings.txt).
41f4d7e6f6STinghan Shen      Required by mt8183 and mt8192.
42f4d7e6f6STinghan Shen    maxItems: 1
43f4d7e6f6STinghan Shen
44f4d7e6f6STinghan Shen  clock-names:
45f4d7e6f6STinghan Shen    const: main
46f4d7e6f6STinghan Shen
47b7da6f51SNícolas F. R. A. Prado  interrupts:
48b7da6f51SNícolas F. R. A. Prado    maxItems: 1
49b7da6f51SNícolas F. R. A. Prado
5031976eb1SAllen-KH Cheng  firmware-name:
51506355c5SKrzysztof Kozlowski    maxItems: 1
5231976eb1SAllen-KH Cheng    description:
5331976eb1SAllen-KH Cheng      If present, name (or relative path) of the file within the
5431976eb1SAllen-KH Cheng      firmware search path containing the firmware image used when
5531976eb1SAllen-KH Cheng      initializing SCP.
5631976eb1SAllen-KH Cheng
57bb489b96SNícolas F. R. A. Prado  memory-region:
58bb489b96SNícolas F. R. A. Prado    maxItems: 1
59bb489b96SNícolas F. R. A. Prado
60cdd22187STinghan Shen  cros-ec-rpmsg:
61cdd22187STinghan Shen    $ref: /schemas/mfd/google,cros-ec.yaml
62cdd22187STinghan Shen    description:
63cdd22187STinghan Shen      This subnode represents the rpmsg device. The properties
64cdd22187STinghan Shen      of this node are defined by the individual bindings for
65cdd22187STinghan Shen      the rpmsg devices.
66cdd22187STinghan Shen
67cdd22187STinghan Shen    required:
68cdd22187STinghan Shen      - mediatek,rpmsg-name
69cdd22187STinghan Shen
70cdd22187STinghan Shen    unevaluatedProperties: false
71cdd22187STinghan Shen
726b55b1e2STinghan Shen  '#address-cells':
736b55b1e2STinghan Shen    const: 1
746b55b1e2STinghan Shen
756b55b1e2STinghan Shen  '#size-cells':
766b55b1e2STinghan Shen    const: 1
776b55b1e2STinghan Shen
786b55b1e2STinghan Shen  ranges:
796b55b1e2STinghan Shen    description:
806b55b1e2STinghan Shen      Standard ranges definition providing address translations for
816b55b1e2STinghan Shen      local SCP SRAM address spaces to bus addresses.
826b55b1e2STinghan Shen
836b55b1e2STinghan ShenpatternProperties:
846b55b1e2STinghan Shen  "^scp@[a-f0-9]+$":
856b55b1e2STinghan Shen    type: object
866b55b1e2STinghan Shen    description:
876b55b1e2STinghan Shen      The MediaTek SCP integrated to SoC might be a multi-core version.
886b55b1e2STinghan Shen      The other cores are represented as child nodes of the boot core.
896b55b1e2STinghan Shen      There are some integration differences for the IP like the usage of
906b55b1e2STinghan Shen      address translator for translating SoC bus addresses into address space
916b55b1e2STinghan Shen      for the processor.
926b55b1e2STinghan Shen
936b55b1e2STinghan Shen      Each SCP core has own cache memory. The SRAM and L1TCM are shared by
946b55b1e2STinghan Shen      cores. The power of cache, SRAM and L1TCM power should be enabled
956b55b1e2STinghan Shen      before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
96*a7fcc232SYu-Chun Lin      on different SoCs.
976b55b1e2STinghan Shen
986b55b1e2STinghan Shen      The SCP cores do not use an MMU, but has a set of registers to
996b55b1e2STinghan Shen      control the translations between 32-bit CPU addresses into system bus
1006b55b1e2STinghan Shen      addresses. Cache and memory access settings are provided through a
1016b55b1e2STinghan Shen      Memory Protection Unit (MPU), programmable only from the SCP.
1026b55b1e2STinghan Shen
1036b55b1e2STinghan Shen    properties:
1046b55b1e2STinghan Shen      compatible:
1056b55b1e2STinghan Shen        enum:
1066b55b1e2STinghan Shen          - mediatek,scp-core
1076b55b1e2STinghan Shen
1086b55b1e2STinghan Shen      reg:
1096b55b1e2STinghan Shen        description: The base address and size of SRAM.
1106b55b1e2STinghan Shen        maxItems: 1
1116b55b1e2STinghan Shen
1126b55b1e2STinghan Shen      reg-names:
1136b55b1e2STinghan Shen        const: sram
1146b55b1e2STinghan Shen
1156b55b1e2STinghan Shen      interrupts:
1166b55b1e2STinghan Shen        maxItems: 1
1176b55b1e2STinghan Shen
1186b55b1e2STinghan Shen      firmware-name:
119506355c5SKrzysztof Kozlowski        maxItems: 1
1206b55b1e2STinghan Shen        description:
1216b55b1e2STinghan Shen          If present, name (or relative path) of the file within the
1226b55b1e2STinghan Shen          firmware search path containing the firmware image used when
1236b55b1e2STinghan Shen          initializing sub cores of multi-core SCP.
1246b55b1e2STinghan Shen
1256b55b1e2STinghan Shen      memory-region:
1266b55b1e2STinghan Shen        maxItems: 1
1276b55b1e2STinghan Shen
1286b55b1e2STinghan Shen      cros-ec-rpmsg:
1296b55b1e2STinghan Shen        $ref: /schemas/mfd/google,cros-ec.yaml
1306b55b1e2STinghan Shen        description:
1316b55b1e2STinghan Shen          This subnode represents the rpmsg device. The properties
1326b55b1e2STinghan Shen          of this node are defined by the individual bindings for
1336b55b1e2STinghan Shen          the rpmsg devices.
1346b55b1e2STinghan Shen
1356b55b1e2STinghan Shen        required:
1366b55b1e2STinghan Shen          - mediatek,rpmsg-name
1376b55b1e2STinghan Shen
1386b55b1e2STinghan Shen        unevaluatedProperties: false
1396b55b1e2STinghan Shen
1406b55b1e2STinghan Shen    required:
1416b55b1e2STinghan Shen      - compatible
1426b55b1e2STinghan Shen      - reg
1436b55b1e2STinghan Shen      - reg-names
1446b55b1e2STinghan Shen
1456b55b1e2STinghan Shen    additionalProperties: false
1466b55b1e2STinghan Shen
147f4d7e6f6STinghan Shenrequired:
148f4d7e6f6STinghan Shen  - compatible
149f4d7e6f6STinghan Shen  - reg
150f4d7e6f6STinghan Shen  - reg-names
151f4d7e6f6STinghan Shen
1526bbe1065SNícolas F. R. A. PradoallOf:
1536bbe1065SNícolas F. R. A. Prado  - if:
154f4d7e6f6STinghan Shen      properties:
155f4d7e6f6STinghan Shen        compatible:
156f4d7e6f6STinghan Shen          enum:
157f4d7e6f6STinghan Shen            - mediatek,mt8183-scp
158f4d7e6f6STinghan Shen            - mediatek,mt8192-scp
159f4d7e6f6STinghan Shen    then:
160f4d7e6f6STinghan Shen      required:
161f4d7e6f6STinghan Shen        - clocks
162f4d7e6f6STinghan Shen        - clock-names
163f4d7e6f6STinghan Shen
1646bbe1065SNícolas F. R. A. Prado  - if:
1656bbe1065SNícolas F. R. A. Prado      properties:
1666bbe1065SNícolas F. R. A. Prado        compatible:
1676bbe1065SNícolas F. R. A. Prado          enum:
1686bbe1065SNícolas F. R. A. Prado            - mediatek,mt8183-scp
1696bbe1065SNícolas F. R. A. Prado            - mediatek,mt8186-scp
17016557244STinghan Shen            - mediatek,mt8188-scp
1716bbe1065SNícolas F. R. A. Prado    then:
1726bbe1065SNícolas F. R. A. Prado      properties:
1736bbe1065SNícolas F. R. A. Prado        reg:
1746bbe1065SNícolas F. R. A. Prado          maxItems: 2
1756bbe1065SNícolas F. R. A. Prado        reg-names:
1766b55b1e2STinghan Shen          items:
1776b55b1e2STinghan Shen            - const: sram
1786b55b1e2STinghan Shen            - const: cfg
1796b55b1e2STinghan Shen  - if:
1806b55b1e2STinghan Shen      properties:
1816b55b1e2STinghan Shen        compatible:
1826b55b1e2STinghan Shen          enum:
1836b55b1e2STinghan Shen            - mediatek,mt8192-scp
1846b55b1e2STinghan Shen            - mediatek,mt8195-scp
1856b55b1e2STinghan Shen    then:
1866b55b1e2STinghan Shen      properties:
1876b55b1e2STinghan Shen        reg:
1886b55b1e2STinghan Shen          maxItems: 3
1896b55b1e2STinghan Shen        reg-names:
1906b55b1e2STinghan Shen          items:
1916b55b1e2STinghan Shen            - const: sram
1926b55b1e2STinghan Shen            - const: cfg
1936b55b1e2STinghan Shen            - const: l1tcm
1946b55b1e2STinghan Shen  - if:
1956b55b1e2STinghan Shen      properties:
1966b55b1e2STinghan Shen        compatible:
1976b55b1e2STinghan Shen          enum:
19891e0d560SOlivia Wen            - mediatek,mt8188-scp-dual
1996b55b1e2STinghan Shen            - mediatek,mt8195-scp-dual
2006b55b1e2STinghan Shen    then:
2016b55b1e2STinghan Shen      properties:
2026b55b1e2STinghan Shen        reg:
2036bbe1065SNícolas F. R. A. Prado          maxItems: 2
2046b55b1e2STinghan Shen        reg-names:
2056b55b1e2STinghan Shen          items:
2066b55b1e2STinghan Shen            - const: cfg
2076b55b1e2STinghan Shen            - const: l1tcm
2086bbe1065SNícolas F. R. A. Prado
209cdd22187STinghan ShenadditionalProperties: false
210f4d7e6f6STinghan Shen
211f4d7e6f6STinghan Shenexamples:
212f4d7e6f6STinghan Shen  - |
2136bbe1065SNícolas F. R. A. Prado    #include <dt-bindings/clock/mt8192-clk.h>
214f4d7e6f6STinghan Shen
215f4d7e6f6STinghan Shen    scp@10500000 {
2166bbe1065SNícolas F. R. A. Prado        compatible = "mediatek,mt8192-scp";
217f4d7e6f6STinghan Shen        reg = <0x10500000 0x80000>,
218f4d7e6f6STinghan Shen              <0x10700000 0x8000>,
219f4d7e6f6STinghan Shen              <0x10720000 0xe0000>;
220f4d7e6f6STinghan Shen        reg-names = "sram", "cfg", "l1tcm";
221f4d7e6f6STinghan Shen        clocks = <&infracfg CLK_INFRA_SCPSYS>;
222f4d7e6f6STinghan Shen        clock-names = "main";
223f4d7e6f6STinghan Shen
224cdd22187STinghan Shen        cros-ec-rpmsg {
225cdd22187STinghan Shen            compatible = "google,cros-ec-rpmsg";
226f4d7e6f6STinghan Shen            mediatek,rpmsg-name = "cros-ec-rpmsg";
227f4d7e6f6STinghan Shen        };
228f4d7e6f6STinghan Shen    };
2296b55b1e2STinghan Shen
2306b55b1e2STinghan Shen  - |
2316b55b1e2STinghan Shen    scp@10500000 {
2326b55b1e2STinghan Shen        compatible = "mediatek,mt8195-scp-dual";
2336b55b1e2STinghan Shen        reg = <0x10720000 0xe0000>,
2346b55b1e2STinghan Shen              <0x10700000 0x8000>;
2356b55b1e2STinghan Shen        reg-names = "cfg", "l1tcm";
2366b55b1e2STinghan Shen
2376b55b1e2STinghan Shen        #address-cells = <1>;
2386b55b1e2STinghan Shen        #size-cells = <1>;
2396b55b1e2STinghan Shen        ranges = <0 0x10500000 0x100000>;
2406b55b1e2STinghan Shen
2416b55b1e2STinghan Shen        scp@0 {
2426b55b1e2STinghan Shen            compatible = "mediatek,scp-core";
2436b55b1e2STinghan Shen            reg = <0x0 0xa0000>;
2446b55b1e2STinghan Shen            reg-names = "sram";
2456b55b1e2STinghan Shen
2466b55b1e2STinghan Shen            cros-ec-rpmsg {
2476b55b1e2STinghan Shen                compatible = "google,cros-ec-rpmsg";
2486b55b1e2STinghan Shen                mediatek,rpmsg-name = "cros-ec-rpmsg";
2496b55b1e2STinghan Shen            };
2506b55b1e2STinghan Shen        };
2516b55b1e2STinghan Shen
2526b55b1e2STinghan Shen        scp@a0000 {
2536b55b1e2STinghan Shen            compatible = "mediatek,scp-core";
2546b55b1e2STinghan Shen            reg = <0xa0000 0x20000>;
2556b55b1e2STinghan Shen            reg-names = "sram";
2566b55b1e2STinghan Shen
2576b55b1e2STinghan Shen            cros-ec-rpmsg {
2586b55b1e2STinghan Shen                compatible = "google,cros-ec-rpmsg";
2596b55b1e2STinghan Shen                mediatek,rpmsg-name = "cros-ec-rpmsg";
2606b55b1e2STinghan Shen            };
2616b55b1e2STinghan Shen        };
2626b55b1e2STinghan Shen    };
263