Lines Matching +full:device +full:- +full:sram
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
20 - #size-cells: should be set to 1.
21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
34 exposes multiple CS lines (multi-dies chips), your reg property will
38 device (always 0)
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
43 - cs-gpios: the GPIO(s) used to control the CS line.
44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
54 - compatible: should be one of the following
55 "atmel,at91sam9g45-pmecc"
56 "atmel,sama5d4-pmecc"
57 "atmel,sama5d2-pmecc"
58 "microchip,sam9x60-pmecc"
59 "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
60 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
65 nfc_io: nfc-io@70000000 {
66 compatible = "atmel,sama5d3-nfc-io", "syscon";
70 pmecc: ecc-engine@ffffc070 {
71 compatible = "atmel,at91sam9g45-pmecc";
77 compatible = "atmel,sama5d3-ebi";
78 #address-cells = <2>;
79 #size-cells = <1>;
89 nand_controller: nand-controller {
90 compatible = "atmel,sama5d3-nand-controller";
91 atmel,nfc-sram = <&nfc_sram>;
92 atmel,nfc-io = <&nfc_io>;
93 ecc-engine = <&pmecc>;
94 #address-cells = <2>;
95 #size-cells = <1>;
110 -----------------------------------------------------------------------
112 Deprecated bindings (should not be used in new device trees):
115 - compatible: The possible values are:
116 "atmel,at91rm9200-nand"
117 "atmel,sama5d2-nand"
118 "atmel,sama5d4-nand"
119 - reg : should specify localbus address and size used for the chip,
125 - atmel,nand-addr-offset : offset for the address latch.
126 - atmel,nand-cmd-offset : offset for the command latch.
127 - #address-cells, #size-cells : Must be present if the device has sub-nodes
130 - gpios : specifies the gpio pins to control the NAND device. detect is an
134 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
135 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
138 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
140 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
142 is "atmel,sama5d2-nand", 32 is also valid.
143 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
145 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
148 - nand-bus-width : 8 or 16 bus width if not present 8
149 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
151 Nand Flash Controller(NFC) is an optional sub-node
153 - compatible : "atmel,sama5d3-nfc".
154 - reg : should specify the address and size used for NFC command registers,
155 NFC registers and NFC SRAM. NFC SRAM address and size can be absent
157 - clocks: phandle to the peripheral clock
159 - atmel,write-by-sram: boolean to enable NFC write by SRAM.
163 compatible = "atmel,at91rm9200-nand";
164 #address-cells = <1>;
165 #size-cells = <1>;
169 atmel,nand-addr-offset = <21>; /* ale */
170 atmel,nand-cmd-offset = <22>; /* cle */
171 nand-on-flash-bbt;
172 nand-ecc-mode = "soft";
184 compatible = "atmel,at91rm9200-nand";
185 #address-cells = <1>;
186 #size-cells = <1>;
192 atmel,nand-addr-offset = <21>; /* ale */
193 atmel,nand-cmd-offset = <22>; /* cle */
194 nand-on-flash-bbt;
195 nand-ecc-mode = "hw";
196 atmel,has-pmecc; /* enable PMECC */
197 atmel,pmecc-cap = <2>;
198 atmel,pmecc-sector-size = <512>;
199 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
211 compatible = "atmel,at91rm9200-nand";
212 #address-cells = <1>;
213 #size-cells = <1>;
217 compatible = "atmel,sama5d3-nfc";
218 #address-cells = <1>;
219 #size-cells = <1>;
224 0x00200000 0x00100000 /* NFC SRAM banks */