Lines Matching +full:device +full:- +full:sram
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 SRAM or NOR) depending on the specific configuration.
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
27 - arm,pl354
29 - compatible
33 pattern: "^memory-controller@[0-9a-f]+$"
37 - enum:
38 - arm,pl353-smc-r2p1
39 - arm,pl354
40 - const: arm,primecell
42 "#address-cells":
45 "#size-cells":
50 - description:
51 Configuration registers for the host and sub-controllers.
58 clock-names:
69 - description: Combined or Memory interface 0 IRQ
70 - description: Memory interface 1 IRQ
73 "@[0-7],[a-f0-9]+$":
77 The child device node represents the controller connected to the SMC
79 mapped controllers such as NOR and SRAM controllers.
88 - items:
89 - description: |
90 Chip-select ID, as in the parent range property.
93 - description: |
94 Offset of the memory region requested by the device.
95 - description: |
96 Length of the memory region requested by the device.
99 - compatible
100 - reg
103 - compatible
104 - reg
105 - clock-names
106 - clocks
111 - if:
122 clock-names:
129 - description: clock for the memory device bus
130 - description: main clock of the SMC
132 clock-names:
134 - const: memclk
135 - const: apb_pclk
138 - |
139 smcc: memory-controller@e000e000 {
140 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
142 clock-names = "memclk", "apb_pclk";
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
147 #address-cells = <2>;
148 #size-cells = <1>;
150 nfc0: nand-controller@0,0 {
151 compatible = "arm,pl353-nand-r2p1";
153 #address-cells = <1>;
154 #size-cells = <0>;