Home
last modified time | relevance | path

Searched full:eyeq5 (Results 1 – 17 of 17) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/mobileye/
H A Dmobileye,eyeq5-olb.yaml4 $id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
16 resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
23 - mobileye,eyeq5-olb
290 - mobileye,eyeq5-olb
313 # Only EyeQ5 has pinctrl in OLB.
319 const: mobileye,eyeq5-olb
331 compatible = "mobileye,eyeq5-olb", "syscon";
/linux/arch/mips/mobileye/
H A DKconfig11 bool "Mobileye EyeQ5 SoC"
18 bool "Include FDT for Mobileye EyeQ5 development platforms"
22 Enable this to include the FDT for the EyeQ5 development platforms
H A Dboard-epm5.its.S6 data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb");
/linux/Documentation/devicetree/bindings/mips/
H A Dmobileye.yaml24 - description: Boards with Mobileye EyeQ5 SoC
27 - mobileye,eyeq5-epm5
28 - const: mobileye,eyeq5
/linux/Documentation/devicetree/bindings/i2c/
H A Dst,nomadik-i2c.yaml24 - mobileye,eyeq5-i2c
35 - mobileye,eyeq5-i2c
98 const: mobileye,eyeq5-i2c
141 compatible = "mobileye,eyeq5-i2c", "arm,primecell";
/linux/drivers/reset/
H A Dreset-eyeq.c3 * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
5 * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
18 * Known resets in EyeQ5 domain 0 (type EQR_EYEQ5_SARCR):
27 * Known resets in EyeQ5 domain 1 (type EQR_EYEQ5_ACRP):
33 * Known resets in EyeQ5 domain 2 (type EQR_EYEQ5_PCIE):
545 { .compatible = "mobileye,eyeq5-olb", .data = &eqr_eyeq5_data },
/linux/arch/mips/boot/dts/mobileye/
H A DMakefile4 dtb-$(CONFIG_MACH_EYEQ5) += eyeq5-epm5.dtb
H A Deyeq5-pins.dtsi4 * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
/linux/drivers/gpio/
H A Dgpio-nomadik.c10 * This driver also handles the mobileye,eyeq5-gpio compatible. It is an STA2X11
556 "mobileye,eyeq5-gpio"); in nmk_gpio_populate_chip()
716 { .compatible = "mobileye,eyeq5-gpio", },
H A DKconfig536 used by the Mobileye EyeQ5 SoC.
/linux/drivers/pinctrl/
H A DKconfig247 bool "Mobileye EyeQ5 pinctrl driver"
255 Pin controller driver for the Mobileye EyeQ5 platform. It does both
H A DMakefile29 obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
H A Dpinctrl-eyeq5.c3 * Pinctrl driver for the Mobileye EyeQ5 platform.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
/linux/drivers/i2c/busses/
H A Di2c-nomadik.c9 * The Mobileye EyeQ5 and EyeQ6H platforms are also supported; they use
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
122 /* Mobileye EyeQ5 offset into a shared register region (called OLB) */
1071 .compatible = "mobileye,eyeq5-i2c",
/linux/arch/mips/
H A DKconfig1035 bool "Include FDT for Mobileye EyeQ5 development platforms"
1039 Enable this to include the FDT for the EyeQ5 development platforms
/linux/drivers/spi/
H A Dspi-cadence-quadspi.c2184 .compatible = "mobileye,eyeq5-ospi",
/linux/
H A DMAINTAINERS17114 F: drivers/pinctrl/pinctrl-eyeq5.c
17116 F: include/dt-bindings/clock/mobileye,eyeq5-clk.h