1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER 361fc4131SPhilipp Zabel bool 461fc4131SPhilipp Zabel 561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER 661fc4131SPhilipp Zabel bool "Reset Controller Support" 761fc4131SPhilipp Zabel default y if ARCH_HAS_RESET_CONTROLLER 861fc4131SPhilipp Zabel help 961fc4131SPhilipp Zabel Generic Reset Controller support. 1061fc4131SPhilipp Zabel 1161fc4131SPhilipp Zabel This framework is designed to abstract reset handling of devices 1261fc4131SPhilipp Zabel via GPIOs or SoC-internal reset controller modules. 1361fc4131SPhilipp Zabel 1461fc4131SPhilipp Zabel If unsure, say no. 15e5d76075SStephen Gallimore 16998cd463SMasahiro Yamadaif RESET_CONTROLLER 17998cd463SMasahiro Yamada 1862700682SThor Thayerconfig RESET_A10SR 1962700682SThor Thayer tristate "Altera Arria10 System Resource Reset" 20af19f193SPhilipp Zabel depends on MFD_ALTERA_A10SR || COMPILE_TEST 2162700682SThor Thayer help 2262700682SThor Thayer This option enables support for the external reset functions for 2362700682SThor Thayer peripheral PHYs on the Altera Arria10 System Resource Chip. 2462700682SThor Thayer 259c50f99cSRyan Chenconfig RESET_ASPEED 269c50f99cSRyan Chen tristate "ASPEED Reset Driver" 279c50f99cSRyan Chen depends on ARCH_ASPEED || COMPILE_TEST 289c50f99cSRyan Chen select AUXILIARY_BUS 299c50f99cSRyan Chen help 309c50f99cSRyan Chen This enables the reset controller driver for AST2700. 319c50f99cSRyan Chen 32e27b4a6eSPhilipp Zabelconfig RESET_ATH79 33e27b4a6eSPhilipp Zabel bool "AR71xx Reset Driver" if COMPILE_TEST 34e27b4a6eSPhilipp Zabel default ATH79 35e27b4a6eSPhilipp Zabel help 36e27b4a6eSPhilipp Zabel This enables the ATH79 reset controller driver that supports the 37e27b4a6eSPhilipp Zabel AR71xx SoC reset controller. 38e27b4a6eSPhilipp Zabel 3937634923SEugeniy Paltsevconfig RESET_AXS10X 4037634923SEugeniy Paltsev bool "AXS10x Reset Driver" if COMPILE_TEST 4137634923SEugeniy Paltsev default ARC_PLAT_AXS10X 4237634923SEugeniy Paltsev help 4337634923SEugeniy Paltsev This enables the reset controller driver for AXS10x. 4437634923SEugeniy Paltsev 45aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345 46aac02543SÁlvaro Fernández Rojas bool "BCM6345 Reset Controller" 47aac02543SÁlvaro Fernández Rojas depends on BMIPS_GENERIC || COMPILE_TEST 48aac02543SÁlvaro Fernández Rojas default BMIPS_GENERIC 49aac02543SÁlvaro Fernández Rojas help 50aac02543SÁlvaro Fernández Rojas This enables the reset controller driver for BCM6345 SoCs. 51aac02543SÁlvaro Fernández Rojas 5270d467eaSPhilipp Zabelconfig RESET_BERLIN 535e787cdfSJisheng Zhang tristate "Berlin Reset Driver" 545e787cdfSJisheng Zhang depends on ARCH_BERLIN || COMPILE_TEST 555e787cdfSJisheng Zhang default m if ARCH_BERLIN 5670d467eaSPhilipp Zabel help 5770d467eaSPhilipp Zabel This enables the reset controller driver for Marvell Berlin SoCs. 5870d467eaSPhilipp Zabel 5977750bc0SFlorian Fainelliconfig RESET_BRCMSTB 6077750bc0SFlorian Fainelli tristate "Broadcom STB reset controller" 611d99f92fSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 621d99f92fSPeter Robinson default ARCH_BRCMSTB || ARCH_BCM2835 6377750bc0SFlorian Fainelli help 6477750bc0SFlorian Fainelli This enables the reset controller driver for Broadcom STB SoCs using 6577750bc0SFlorian Fainelli a SUN_TOP_CTRL_SW_INIT style controller. 6677750bc0SFlorian Fainelli 674cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL 685694ca29SFlorian Fainelli tristate "Broadcom STB RESCAL reset controller" 697fbcc535SBrendan Higgins depends on HAS_IOMEM 701d99f92fSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 711d99f92fSPeter Robinson default ARCH_BRCMSTB || ARCH_BCM2835 724cf176e5SJim Quinlan help 734cf176e5SJim Quinlan This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 741d99f92fSPeter Robinson BCM7216 or the BCM2712. 754cf176e5SJim Quinlan 760884bd97SXuyang Dongconfig RESET_EIC7700 770884bd97SXuyang Dong bool "Reset controller driver for ESWIN SoCs" 780884bd97SXuyang Dong depends on ARCH_ESWIN || COMPILE_TEST 790884bd97SXuyang Dong default ARCH_ESWIN 800884bd97SXuyang Dong help 810884bd97SXuyang Dong This enables the reset controller driver for ESWIN SoCs. This driver is 820884bd97SXuyang Dong specific to ESWIN SoCs and should only be enabled if using such hardware. 830884bd97SXuyang Dong The driver supports eic7700 series chips and provides functionality for 840884bd97SXuyang Dong asserting and deasserting resets on the chip. 850884bd97SXuyang Dong 86487b1b32SThéo Lebrunconfig RESET_EYEQ 87487b1b32SThéo Lebrun bool "Mobileye EyeQ reset controller" 88487b1b32SThéo Lebrun depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 89487b1b32SThéo Lebrun select AUXILIARY_BUS 90487b1b32SThéo Lebrun default MACH_EYEQ5 || MACH_EYEQ6H 91487b1b32SThéo Lebrun help 92487b1b32SThéo Lebrun This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 93487b1b32SThéo Lebrun and EyeQ6H SoCs. 94487b1b32SThéo Lebrun 95487b1b32SThéo Lebrun It has one or more domains, with a varying number of resets in each. 96487b1b32SThéo Lebrun Registers are located in a shared register region called OLB. EyeQ6H 97487b1b32SThéo Lebrun has multiple reset instances. 98487b1b32SThéo Lebrun 99cee544a4SKrzysztof Kozlowskiconfig RESET_GPIO 100cee544a4SKrzysztof Kozlowski tristate "GPIO reset controller" 10101f6a84cSMark Brown depends on GPIOLIB 102109ce747SBartosz Golaszewski select AUXILIARY_BUS 103cee544a4SKrzysztof Kozlowski help 104cee544a4SKrzysztof Kozlowski This enables a generic reset controller for resets attached via 105cee544a4SKrzysztof Kozlowski GPIOs. Typically for OF platforms this driver expects "reset-gpios" 106cee544a4SKrzysztof Kozlowski property. 107cee544a4SKrzysztof Kozlowski 108cee544a4SKrzysztof Kozlowski If compiled as module, it will be called reset-gpio. 109cee544a4SKrzysztof Kozlowski 11013541226SVineet Guptaconfig RESET_HSDK 11113541226SVineet Gupta bool "Synopsys HSDK Reset Driver" 1122d48a237SThomas Meyer depends on HAS_IOMEM 113544e3bf4SGeert Uytterhoeven depends on ARC_SOC_HSDK || COMPILE_TEST 114e0be864fSEugeniy Paltsev help 11513541226SVineet Gupta This enables the reset controller driver for HSDK board. 116e0be864fSEugeniy Paltsev 1176b64fde5SFrank Liconfig RESET_IMX_SCU 1186b64fde5SFrank Li tristate "i.MX8Q Reset Driver" 1196b64fde5SFrank Li depends on IMX_SCU && HAVE_ARM_SMCCC 1206b64fde5SFrank Li depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 1216b64fde5SFrank Li help 1226b64fde5SFrank Li This enables the reset controller driver for i.MX8QM/i.MX8QXP 1236b64fde5SFrank Li 124abf97755SAndrey Smirnovconfig RESET_IMX7 125a442abbbSAnson Huang tristate "i.MX7/8 Reset Driver" 1268fa56620SMasahiro Yamada depends on HAS_IOMEM 127a442abbbSAnson Huang depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 128a442abbbSAnson Huang default y if SOC_IMX7D 129abf97755SAndrey Smirnov select MFD_SYSCON 130abf97755SAndrey Smirnov help 131abf97755SAndrey Smirnov This enables the reset controller driver for i.MX7 SoCs. 132abf97755SAndrey Smirnov 133fe125601SShengjiu Wangconfig RESET_IMX8MP_AUDIOMIX 134fe125601SShengjiu Wang tristate "i.MX8MP AudioMix Reset Driver" 135eb5d88b1SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 136fe125601SShengjiu Wang select AUXILIARY_BUS 137fe125601SShengjiu Wang default CLK_IMX8MP 138fe125601SShengjiu Wang help 139fe125601SShengjiu Wang This enables the reset controller driver for i.MX8MP AudioMix 140fe125601SShengjiu Wang 141c9aef213SDilip Kotaconfig RESET_INTEL_GW 142c9aef213SDilip Kota bool "Intel Reset Controller Driver" 1436ab9d621SGeert Uytterhoeven depends on X86 || COMPILE_TEST 144b460e0a9SBrendan Higgins depends on OF && HAS_IOMEM 145c9aef213SDilip Kota select REGMAP_MMIO 146c9aef213SDilip Kota help 147c9aef213SDilip Kota This enables the reset controller driver for Intel Gateway SoCs. 148c9aef213SDilip Kota Say Y to control the reset signals provided by reset controller. 149c9aef213SDilip Kota Otherwise, say N. 150c9aef213SDilip Kota 1515a2308daSDamien Le Moalconfig RESET_K210 1525a2308daSDamien Le Moal bool "Reset controller driver for Canaan Kendryte K210 SoC" 15368f41105SYangyu Chen depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 1545a2308daSDamien Le Moal select MFD_SYSCON 15568f41105SYangyu Chen default SOC_CANAAN_K210 1565a2308daSDamien Le Moal help 1575a2308daSDamien Le Moal Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 1585a2308daSDamien Le Moal Say Y if you want to control reset signals provided by this 1595a2308daSDamien Le Moal controller. 1605a2308daSDamien Le Moal 161360a7a64SJunhui Liuconfig RESET_K230 162360a7a64SJunhui Liu tristate "Reset controller driver for Canaan Kendryte K230 SoC" 163360a7a64SJunhui Liu depends on ARCH_CANAAN || COMPILE_TEST 164360a7a64SJunhui Liu depends on OF 165360a7a64SJunhui Liu help 166360a7a64SJunhui Liu Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 167360a7a64SJunhui Liu Say Y if you want to control reset signals provided by this 168360a7a64SJunhui Liu controller. 169360a7a64SJunhui Liu 17079797b6fSMartin Blumenstinglconfig RESET_LANTIQ 17179797b6fSMartin Blumenstingl bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 17279797b6fSMartin Blumenstingl default SOC_TYPE_XWAY 17379797b6fSMartin Blumenstingl help 17479797b6fSMartin Blumenstingl This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 17579797b6fSMartin Blumenstingl 176cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX 177cd7f4b81SPhilipp Zabel bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 178cd7f4b81SPhilipp Zabel default ARCH_LPC18XX 179cd7f4b81SPhilipp Zabel help 180cd7f4b81SPhilipp Zabel This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 181cd7f4b81SPhilipp Zabel 182453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5 183996737efSClément Léger tristate "Microchip Sparx5 reset driver" 184bf919ccfSRobert Marko depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 185453ed428SSteen Hegelund default y if SPARX5_SWITCH 186453ed428SSteen Hegelund select MFD_SYSCON 187453ed428SSteen Hegelund help 188453ed428SSteen Hegelund This driver supports switch core reset for the Microchip Sparx5 SoC. 189453ed428SSteen Hegelund 1909c81b2ccSTomer Maimonconfig RESET_NPCM 1919c81b2ccSTomer Maimon bool "NPCM BMC Reset Driver" if COMPILE_TEST 1929c81b2ccSTomer Maimon default ARCH_NPCM 19322823157STomer Maimon select AUXILIARY_BUS 1949c81b2ccSTomer Maimon help 1959c81b2ccSTomer Maimon This enables the reset controller driver for Nuvoton NPCM 1969c81b2ccSTomer Maimon BMC SoCs. 1979c81b2ccSTomer Maimon 198e4bb55d6SJacky Huangconfig RESET_NUVOTON_MA35D1 199aead1076SGeert Uytterhoeven bool "Nuvoton MA35D1 Reset Driver" 200aead1076SGeert Uytterhoeven depends on ARCH_MA35 || COMPILE_TEST 201aead1076SGeert Uytterhoeven default ARCH_MA35 202e4bb55d6SJacky Huang help 203e4bb55d6SJacky Huang This enables the reset controller driver for Nuvoton MA35D1 SoC. 204e4bb55d6SJacky Huang 205fab3f730SPhilipp Zabelconfig RESET_PISTACHIO 2064af16070SGeert Uytterhoeven bool "Pistachio Reset Driver" 2074af16070SGeert Uytterhoeven depends on MIPS || COMPILE_TEST 208fab3f730SPhilipp Zabel help 209fab3f730SPhilipp Zabel This enables the reset driver for ImgTec Pistachio SoCs. 210fab3f730SPhilipp Zabel 21105f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC 21205f9e363SConor Dooley bool "Microchip PolarFire SoC (MPFS) Reset Driver" 213afb39e2bSPhilipp Zabel depends on MCHP_CLK_MPFS 214*781f60e4SConor Dooley depends on MFD_SYSCON 215afb39e2bSPhilipp Zabel select AUXILIARY_BUS 21605f9e363SConor Dooley default MCHP_CLK_MPFS 21705f9e363SConor Dooley help 21805f9e363SConor Dooley This driver supports peripheral reset for the Microchip PolarFire SoC 21905f9e363SConor Dooley 2205ecb0651SSibi Sankarconfig RESET_QCOM_AOSS 221e2d5e833SJohn Stultz tristate "Qcom AOSS Reset Driver" 2225ecb0651SSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 2235ecb0651SSibi Sankar help 2245ecb0651SSibi Sankar This enables the AOSS (always on subsystem) reset driver 2255ecb0651SSibi Sankar for Qualcomm SDM845 SoCs. Say Y if you want to control 2265ecb0651SSibi Sankar reset signals provided by AOSS for Modem, Venus, ADSP, 2275ecb0651SSibi Sankar GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 2285ecb0651SSibi Sankar 229eea2926bSSibi Sankarconfig RESET_QCOM_PDC 230eea2926bSSibi Sankar tristate "Qualcomm PDC Reset Driver" 231eea2926bSSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 232eea2926bSSibi Sankar help 233eea2926bSSibi Sankar This enables the PDC (Power Domain Controller) reset driver 234eea2926bSSibi Sankar for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 235eea2926bSSibi Sankar to control reset signals provided by PDC for Modem, Compute, 236eea2926bSSibi Sankar Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 237eea2926bSSibi Sankar 238abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI 239abffc82aSNicolas Saenz Julienne tristate "Raspberry Pi 4 Firmware Reset Driver" 240abffc82aSNicolas Saenz Julienne depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 241abffc82aSNicolas Saenz Julienne default USB_XHCI_PCI 242abffc82aSNicolas Saenz Julienne help 243abffc82aSNicolas Saenz Julienne Raspberry Pi 4's co-processor controls some of the board's HW 244abffc82aSNicolas Saenz Julienne initialization process, but it's up to Linux to trigger it when 245abffc82aSNicolas Saenz Julienne relevant. This driver provides a reset controller capable of 246abffc82aSNicolas Saenz Julienne interfacing with RPi4's co-processor and model these firmware 247abffc82aSNicolas Saenz Julienne initialization routines as reset lines. 248abffc82aSNicolas Saenz Julienne 249bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL 250bee08559SBiju Das tristate "Renesas RZ/G2L USBPHY control driver" 2519fe7dd4eSLad Prabhakar depends on ARCH_RZG2L || COMPILE_TEST 25278f2d64eSClaudiu Beznea select MFD_SYSCON 253bee08559SBiju Das help 254bee08559SBiju Das Support for USBPHY Control found on RZ/G2L family. It mainly 255bee08559SBiju Das controls reset and power down of the USB/PHY. 256bee08559SBiju Das 257e3911d7fSLad Prabhakarconfig RESET_RZV2H_USB2PHY 258e3911d7fSLad Prabhakar tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 259e3911d7fSLad Prabhakar depends on ARCH_RENESAS || COMPILE_TEST 260e3911d7fSLad Prabhakar help 261e3911d7fSLad Prabhakar Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 262e3911d7fSLad Prabhakar (and similar SoCs). 263e3911d7fSLad Prabhakar 264c8ae9c2dSSudeep Hollaconfig RESET_SCMI 265c8ae9c2dSSudeep Holla tristate "Reset driver controlled via ARM SCMI interface" 266c8ae9c2dSSudeep Holla depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 267c8ae9c2dSSudeep Holla default ARM_SCMI_PROTOCOL 268c8ae9c2dSSudeep Holla help 269c8ae9c2dSSudeep Holla This driver provides support for reset signal/domains that are 270c8ae9c2dSSudeep Holla controlled by firmware that implements the SCMI interface. 271c8ae9c2dSSudeep Holla 272c8ae9c2dSSudeep Holla This driver uses SCMI Message Protocol to interact with the 273c8ae9c2dSSudeep Holla firmware controlling all the reset signals. 274c8ae9c2dSSudeep Holla 27581c22ad0SPhilipp Zabelconfig RESET_SIMPLE 27618d1909bSBen Dooks bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 277a6166a4dSChen Wang default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 278c4ada3caSBen Dooks depends on HAS_IOMEM 27981c22ad0SPhilipp Zabel help 28081c22ad0SPhilipp Zabel This enables a simple reset controller driver for reset lines that 28181c22ad0SPhilipp Zabel that can be asserted and deasserted by toggling bits in a contiguous, 28281c22ad0SPhilipp Zabel exclusive register space. 28381c22ad0SPhilipp Zabel 2841d7592f8SJoel Stanley Currently this driver supports: 2851d7592f8SJoel Stanley - Altera SoCFPGAs 2861d7592f8SJoel Stanley - ASPEED BMC SoCs 2875ac33eebSAndreas Färber - Bitmain BM1880 SoC 2883ab831e5SAndreas Färber - Realtek SoCs 2891d7592f8SJoel Stanley - RCC reset controller in STM32 MCUs 2901d7592f8SJoel Stanley - Allwinner SoCs 291e4d368e0SGreentime Hu - SiFive FU740 SoCs 292a6166a4dSChen Wang - Sophgo SoCs 2937e0e901dSPhilipp Zabel 294b3ca9888SDinh Nguyenconfig RESET_SOCFPGA 295225c13f0SKrzysztof Kozlowski bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 296225c13f0SKrzysztof Kozlowski default ARM && ARCH_INTEL_SOCFPGA 297b3ca9888SDinh Nguyen select RESET_SIMPLE 298b3ca9888SDinh Nguyen help 299b3ca9888SDinh Nguyen This enables the reset driver for the SoCFPGA ARMv7 platforms. This 300b3ca9888SDinh Nguyen driver gets initialized early during platform init calls. 301b3ca9888SDinh Nguyen 302c479d7cfSAlex Elderconfig RESET_SPACEMIT 303c479d7cfSAlex Elder tristate "SpacemiT reset driver" 304c479d7cfSAlex Elder depends on ARCH_SPACEMIT || COMPILE_TEST 305c479d7cfSAlex Elder select AUXILIARY_BUS 306c479d7cfSAlex Elder default ARCH_SPACEMIT 307c479d7cfSAlex Elder help 308c479d7cfSAlex Elder This enables the reset controller driver for SpacemiT SoCs, 309c479d7cfSAlex Elder including the K1. 310c479d7cfSAlex Elder 311dbf018beSQin Jianconfig RESET_SUNPLUS 312dbf018beSQin Jian bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 313dbf018beSQin Jian default ARCH_SUNPLUS 314dbf018beSQin Jian help 315dbf018beSQin Jian This enables the reset driver support for Sunplus SoCs. 316dbf018beSQin Jian The reset lines that can be asserted and deasserted by toggling bits 317dbf018beSQin Jian in a contiguous, exclusive register space. The register is HIWORD_MASKED, 318dbf018beSQin Jian which means each register holds 16 reset lines. 319dbf018beSQin Jian 3200ae08419SPhilipp Zabelconfig RESET_SUNXI 3210ae08419SPhilipp Zabel bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 3220ae08419SPhilipp Zabel default ARCH_SUNXI 323e13c205aSPhilipp Zabel select RESET_SIMPLE 3240ae08419SPhilipp Zabel help 3250ae08419SPhilipp Zabel This enables the reset driver for Allwinner SoCs. 3260ae08419SPhilipp Zabel 3274a653263SMichal Wilczynskiconfig RESET_TH1520 328e73bfb4cSDrew Fustini tristate "T-HEAD TH1520 reset controller" 3294a653263SMichal Wilczynski depends on ARCH_THEAD || COMPILE_TEST 3304a653263SMichal Wilczynski select REGMAP_MMIO 3314a653263SMichal Wilczynski help 3324a653263SMichal Wilczynski This driver provides support for the T-HEAD TH1520 SoC reset controller, 3334a653263SMichal Wilczynski which manages hardware reset lines for SoC components such as the GPU. 3344a653263SMichal Wilczynski Enable this option if you need to control hardware resets on TH1520-based 3354a653263SMichal Wilczynski systems. 3364a653263SMichal Wilczynski 33728df169bSAndrew F. Davisconfig RESET_TI_SCI 33828df169bSAndrew F. Davis tristate "TI System Control Interface (TI-SCI) reset driver" 33913678f3fSRandy Dunlap depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 34028df169bSAndrew F. Davis help 34128df169bSAndrew F. Davis This enables the reset driver support over TI System Control Interface 34228df169bSAndrew F. Davis available on some new TI's SoCs. If you wish to use reset resources 34328df169bSAndrew F. Davis managed by the TI System Controller, say Y here. Otherwise, say N. 34428df169bSAndrew F. Davis 345dd9bf863SSuman Annaconfig RESET_TI_SYSCON 346cc7c2bb1SAndrew F. Davis tristate "TI SYSCON Reset Driver" 347cc7c2bb1SAndrew F. Davis depends on HAS_IOMEM 348cc7c2bb1SAndrew F. Davis select MFD_SYSCON 349cc7c2bb1SAndrew F. Davis help 350cc7c2bb1SAndrew F. Davis This enables the reset driver support for TI devices with 351cc7c2bb1SAndrew F. Davis memory-mapped reset registers as part of a syscon device node. If 352cc7c2bb1SAndrew F. Davis you wish to use the reset framework for such memory-mapped devices, 353cc7c2bb1SAndrew F. Davis say Y here. Otherwise, say N. 354cc7c2bb1SAndrew F. Davis 3558a4e6154SMarco Felschconfig RESET_TI_TPS380X 3568a4e6154SMarco Felsch tristate "TI TPS380x Reset Driver" 3578a4e6154SMarco Felsch select GPIOLIB 3588a4e6154SMarco Felsch help 3598a4e6154SMarco Felsch This enables the reset driver support for TI TPS380x devices. If 3608a4e6154SMarco Felsch you wish to use the reset framework for such devices, say Y here. 3618a4e6154SMarco Felsch Otherwise, say N. 3628a4e6154SMarco Felsch 3635cd3921dSRobert Markoconfig RESET_TN48M_CPLD 3645cd3921dSRobert Marko tristate "Delta Networks TN48M switch CPLD reset controller" 3655cd3921dSRobert Marko depends on MFD_TN48M_CPLD || COMPILE_TEST 3665cd3921dSRobert Marko default MFD_TN48M_CPLD 3675cd3921dSRobert Marko help 3685cd3921dSRobert Marko This enables the reset controller driver for the Delta TN48M CPLD. 3695cd3921dSRobert Marko It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 3705cd3921dSRobert Marko switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 3715cd3921dSRobert Marko Microchip PD69200 PoE PSE controller. 3725cd3921dSRobert Marko 3735cd3921dSRobert Marko This driver can also be built as a module. If so, the module will be 3745cd3921dSRobert Marko called reset-tn48m. 3755cd3921dSRobert Marko 37654e991b5SMasahiro Yamadaconfig RESET_UNIPHIER 37754e991b5SMasahiro Yamada tristate "Reset controller driver for UniPhier SoCs" 37854e991b5SMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 37954e991b5SMasahiro Yamada depends on OF && MFD_SYSCON 38054e991b5SMasahiro Yamada default ARCH_UNIPHIER 38154e991b5SMasahiro Yamada help 38254e991b5SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 38354e991b5SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 38454e991b5SMasahiro Yamada block, Media I/O block, Peripheral Block. 38554e991b5SMasahiro Yamada 3863eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE 3873eb8f765SKunihiko Hayashi tristate "Reset driver in glue layer for UniPhier SoCs" 388499fef09SKunihiko Hayashi depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 389499fef09SKunihiko Hayashi default ARCH_UNIPHIER 390499fef09SKunihiko Hayashi select RESET_SIMPLE 391499fef09SKunihiko Hayashi help 3923eb8f765SKunihiko Hayashi Support for peripheral core reset included in its own glue layer 3933eb8f765SKunihiko Hayashi on UniPhier SoCs. Say Y if you want to control reset signals 3943eb8f765SKunihiko Hayashi provided by the glue layer. 395499fef09SKunihiko Hayashi 3966f51b860SPhilipp Zabelconfig RESET_ZYNQ 3976f51b860SPhilipp Zabel bool "ZYNQ Reset Driver" if COMPILE_TEST 3986f51b860SPhilipp Zabel default ARCH_ZYNQ 3996f51b860SPhilipp Zabel help 4006f51b860SPhilipp Zabel This enables the reset controller driver for Xilinx Zynq SoCs. 4016f51b860SPhilipp Zabel 4024f6a43adSPhilipp Zabelconfig RESET_ZYNQMP 4034f6a43adSPhilipp Zabel bool "ZYNQMP Reset Driver" if COMPILE_TEST 4044f6a43adSPhilipp Zabel default ARCH_ZYNQMP 4054f6a43adSPhilipp Zabel help 4064f6a43adSPhilipp Zabel This enables the reset controller driver for Xilinx ZynqMP SoCs. 4074f6a43adSPhilipp Zabel 4082c138ee3SJerome Brunetsource "drivers/reset/amlogic/Kconfig" 40969bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig" 410e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig" 411f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig" 412dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig" 413998cd463SMasahiro Yamada 414998cd463SMasahiro Yamadaendif 415