1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER 361fc4131SPhilipp Zabel bool 461fc4131SPhilipp Zabel 561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER 661fc4131SPhilipp Zabel bool "Reset Controller Support" 761fc4131SPhilipp Zabel default y if ARCH_HAS_RESET_CONTROLLER 861fc4131SPhilipp Zabel help 961fc4131SPhilipp Zabel Generic Reset Controller support. 1061fc4131SPhilipp Zabel 1161fc4131SPhilipp Zabel This framework is designed to abstract reset handling of devices 1261fc4131SPhilipp Zabel via GPIOs or SoC-internal reset controller modules. 1361fc4131SPhilipp Zabel 1461fc4131SPhilipp Zabel If unsure, say no. 15e5d76075SStephen Gallimore 16998cd463SMasahiro Yamadaif RESET_CONTROLLER 17998cd463SMasahiro Yamada 1862700682SThor Thayerconfig RESET_A10SR 1962700682SThor Thayer tristate "Altera Arria10 System Resource Reset" 20af19f193SPhilipp Zabel depends on MFD_ALTERA_A10SR || COMPILE_TEST 2162700682SThor Thayer help 2262700682SThor Thayer This option enables support for the external reset functions for 2362700682SThor Thayer peripheral PHYs on the Altera Arria10 System Resource Chip. 2462700682SThor Thayer 25*decdff7dSRyan Chenconfig RESET_ASPEED 26*decdff7dSRyan Chen tristate "ASPEED Reset Driver" 27*decdff7dSRyan Chen depends on ARCH_ASPEED || COMPILE_TEST 28*decdff7dSRyan Chen select AUXILIARY_BUS 29*decdff7dSRyan Chen help 30*decdff7dSRyan Chen This enables the reset controller driver for AST2700. 31*decdff7dSRyan Chen 32e27b4a6eSPhilipp Zabelconfig RESET_ATH79 33e27b4a6eSPhilipp Zabel bool "AR71xx Reset Driver" if COMPILE_TEST 34e27b4a6eSPhilipp Zabel default ATH79 35e27b4a6eSPhilipp Zabel help 36e27b4a6eSPhilipp Zabel This enables the ATH79 reset controller driver that supports the 37e27b4a6eSPhilipp Zabel AR71xx SoC reset controller. 38e27b4a6eSPhilipp Zabel 3937634923SEugeniy Paltsevconfig RESET_AXS10X 4037634923SEugeniy Paltsev bool "AXS10x Reset Driver" if COMPILE_TEST 4137634923SEugeniy Paltsev default ARC_PLAT_AXS10X 4237634923SEugeniy Paltsev help 4337634923SEugeniy Paltsev This enables the reset controller driver for AXS10x. 4437634923SEugeniy Paltsev 45aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345 46aac02543SÁlvaro Fernández Rojas bool "BCM6345 Reset Controller" 47aac02543SÁlvaro Fernández Rojas depends on BMIPS_GENERIC || COMPILE_TEST 48aac02543SÁlvaro Fernández Rojas default BMIPS_GENERIC 49aac02543SÁlvaro Fernández Rojas help 50aac02543SÁlvaro Fernández Rojas This enables the reset controller driver for BCM6345 SoCs. 51aac02543SÁlvaro Fernández Rojas 5270d467eaSPhilipp Zabelconfig RESET_BERLIN 535e787cdfSJisheng Zhang tristate "Berlin Reset Driver" 545e787cdfSJisheng Zhang depends on ARCH_BERLIN || COMPILE_TEST 555e787cdfSJisheng Zhang default m if ARCH_BERLIN 5670d467eaSPhilipp Zabel help 5770d467eaSPhilipp Zabel This enables the reset controller driver for Marvell Berlin SoCs. 5870d467eaSPhilipp Zabel 5977750bc0SFlorian Fainelliconfig RESET_BRCMSTB 6077750bc0SFlorian Fainelli tristate "Broadcom STB reset controller" 611d99f92fSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 621d99f92fSPeter Robinson default ARCH_BRCMSTB || ARCH_BCM2835 6377750bc0SFlorian Fainelli help 6477750bc0SFlorian Fainelli This enables the reset controller driver for Broadcom STB SoCs using 6577750bc0SFlorian Fainelli a SUN_TOP_CTRL_SW_INIT style controller. 6677750bc0SFlorian Fainelli 674cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL 685694ca29SFlorian Fainelli tristate "Broadcom STB RESCAL reset controller" 697fbcc535SBrendan Higgins depends on HAS_IOMEM 701d99f92fSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 711d99f92fSPeter Robinson default ARCH_BRCMSTB || ARCH_BCM2835 724cf176e5SJim Quinlan help 734cf176e5SJim Quinlan This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 741d99f92fSPeter Robinson BCM7216 or the BCM2712. 754cf176e5SJim Quinlan 76487b1b32SThéo Lebrunconfig RESET_EYEQ 77487b1b32SThéo Lebrun bool "Mobileye EyeQ reset controller" 78487b1b32SThéo Lebrun depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST 79487b1b32SThéo Lebrun select AUXILIARY_BUS 80487b1b32SThéo Lebrun default MACH_EYEQ5 || MACH_EYEQ6H 81487b1b32SThéo Lebrun help 82487b1b32SThéo Lebrun This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L 83487b1b32SThéo Lebrun and EyeQ6H SoCs. 84487b1b32SThéo Lebrun 85487b1b32SThéo Lebrun It has one or more domains, with a varying number of resets in each. 86487b1b32SThéo Lebrun Registers are located in a shared register region called OLB. EyeQ6H 87487b1b32SThéo Lebrun has multiple reset instances. 88487b1b32SThéo Lebrun 89cee544a4SKrzysztof Kozlowskiconfig RESET_GPIO 90cee544a4SKrzysztof Kozlowski tristate "GPIO reset controller" 9101f6a84cSMark Brown depends on GPIOLIB 92cee544a4SKrzysztof Kozlowski help 93cee544a4SKrzysztof Kozlowski This enables a generic reset controller for resets attached via 94cee544a4SKrzysztof Kozlowski GPIOs. Typically for OF platforms this driver expects "reset-gpios" 95cee544a4SKrzysztof Kozlowski property. 96cee544a4SKrzysztof Kozlowski 97cee544a4SKrzysztof Kozlowski If compiled as module, it will be called reset-gpio. 98cee544a4SKrzysztof Kozlowski 9913541226SVineet Guptaconfig RESET_HSDK 10013541226SVineet Gupta bool "Synopsys HSDK Reset Driver" 1012d48a237SThomas Meyer depends on HAS_IOMEM 102544e3bf4SGeert Uytterhoeven depends on ARC_SOC_HSDK || COMPILE_TEST 103e0be864fSEugeniy Paltsev help 10413541226SVineet Gupta This enables the reset controller driver for HSDK board. 105e0be864fSEugeniy Paltsev 1066b64fde5SFrank Liconfig RESET_IMX_SCU 1076b64fde5SFrank Li tristate "i.MX8Q Reset Driver" 1086b64fde5SFrank Li depends on IMX_SCU && HAVE_ARM_SMCCC 1096b64fde5SFrank Li depends on (ARM64 && ARCH_MXC) || COMPILE_TEST 1106b64fde5SFrank Li help 1116b64fde5SFrank Li This enables the reset controller driver for i.MX8QM/i.MX8QXP 1126b64fde5SFrank Li 113abf97755SAndrey Smirnovconfig RESET_IMX7 114a442abbbSAnson Huang tristate "i.MX7/8 Reset Driver" 1158fa56620SMasahiro Yamada depends on HAS_IOMEM 116a442abbbSAnson Huang depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 117a442abbbSAnson Huang default y if SOC_IMX7D 118abf97755SAndrey Smirnov select MFD_SYSCON 119abf97755SAndrey Smirnov help 120abf97755SAndrey Smirnov This enables the reset controller driver for i.MX7 SoCs. 121abf97755SAndrey Smirnov 122fe125601SShengjiu Wangconfig RESET_IMX8MP_AUDIOMIX 123fe125601SShengjiu Wang tristate "i.MX8MP AudioMix Reset Driver" 124eb5d88b1SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 125fe125601SShengjiu Wang select AUXILIARY_BUS 126fe125601SShengjiu Wang default CLK_IMX8MP 127fe125601SShengjiu Wang help 128fe125601SShengjiu Wang This enables the reset controller driver for i.MX8MP AudioMix 129fe125601SShengjiu Wang 130c9aef213SDilip Kotaconfig RESET_INTEL_GW 131c9aef213SDilip Kota bool "Intel Reset Controller Driver" 1326ab9d621SGeert Uytterhoeven depends on X86 || COMPILE_TEST 133b460e0a9SBrendan Higgins depends on OF && HAS_IOMEM 134c9aef213SDilip Kota select REGMAP_MMIO 135c9aef213SDilip Kota help 136c9aef213SDilip Kota This enables the reset controller driver for Intel Gateway SoCs. 137c9aef213SDilip Kota Say Y to control the reset signals provided by reset controller. 138c9aef213SDilip Kota Otherwise, say N. 139c9aef213SDilip Kota 1405a2308daSDamien Le Moalconfig RESET_K210 1415a2308daSDamien Le Moal bool "Reset controller driver for Canaan Kendryte K210 SoC" 14268f41105SYangyu Chen depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 1435a2308daSDamien Le Moal select MFD_SYSCON 14468f41105SYangyu Chen default SOC_CANAAN_K210 1455a2308daSDamien Le Moal help 1465a2308daSDamien Le Moal Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 1475a2308daSDamien Le Moal Say Y if you want to control reset signals provided by this 1485a2308daSDamien Le Moal controller. 1495a2308daSDamien Le Moal 150360a7a64SJunhui Liuconfig RESET_K230 151360a7a64SJunhui Liu tristate "Reset controller driver for Canaan Kendryte K230 SoC" 152360a7a64SJunhui Liu depends on ARCH_CANAAN || COMPILE_TEST 153360a7a64SJunhui Liu depends on OF 154360a7a64SJunhui Liu help 155360a7a64SJunhui Liu Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 156360a7a64SJunhui Liu Say Y if you want to control reset signals provided by this 157360a7a64SJunhui Liu controller. 158360a7a64SJunhui Liu 15979797b6fSMartin Blumenstinglconfig RESET_LANTIQ 16079797b6fSMartin Blumenstingl bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 16179797b6fSMartin Blumenstingl default SOC_TYPE_XWAY 16279797b6fSMartin Blumenstingl help 16379797b6fSMartin Blumenstingl This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 16479797b6fSMartin Blumenstingl 165cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX 166cd7f4b81SPhilipp Zabel bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 167cd7f4b81SPhilipp Zabel default ARCH_LPC18XX 168cd7f4b81SPhilipp Zabel help 169cd7f4b81SPhilipp Zabel This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 170cd7f4b81SPhilipp Zabel 171453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5 172996737efSClément Léger tristate "Microchip Sparx5 reset driver" 173eba0deddSHerve Codina depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 174453ed428SSteen Hegelund default y if SPARX5_SWITCH 175453ed428SSteen Hegelund select MFD_SYSCON 176453ed428SSteen Hegelund help 177453ed428SSteen Hegelund This driver supports switch core reset for the Microchip Sparx5 SoC. 178453ed428SSteen Hegelund 1799c81b2ccSTomer Maimonconfig RESET_NPCM 1809c81b2ccSTomer Maimon bool "NPCM BMC Reset Driver" if COMPILE_TEST 1819c81b2ccSTomer Maimon default ARCH_NPCM 18222823157STomer Maimon select AUXILIARY_BUS 1839c81b2ccSTomer Maimon help 1849c81b2ccSTomer Maimon This enables the reset controller driver for Nuvoton NPCM 1859c81b2ccSTomer Maimon BMC SoCs. 1869c81b2ccSTomer Maimon 187e4bb55d6SJacky Huangconfig RESET_NUVOTON_MA35D1 188aead1076SGeert Uytterhoeven bool "Nuvoton MA35D1 Reset Driver" 189aead1076SGeert Uytterhoeven depends on ARCH_MA35 || COMPILE_TEST 190aead1076SGeert Uytterhoeven default ARCH_MA35 191e4bb55d6SJacky Huang help 192e4bb55d6SJacky Huang This enables the reset controller driver for Nuvoton MA35D1 SoC. 193e4bb55d6SJacky Huang 194fab3f730SPhilipp Zabelconfig RESET_PISTACHIO 1954af16070SGeert Uytterhoeven bool "Pistachio Reset Driver" 1964af16070SGeert Uytterhoeven depends on MIPS || COMPILE_TEST 197fab3f730SPhilipp Zabel help 198fab3f730SPhilipp Zabel This enables the reset driver for ImgTec Pistachio SoCs. 199fab3f730SPhilipp Zabel 20005f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC 20105f9e363SConor Dooley bool "Microchip PolarFire SoC (MPFS) Reset Driver" 202afb39e2bSPhilipp Zabel depends on MCHP_CLK_MPFS 203afb39e2bSPhilipp Zabel select AUXILIARY_BUS 20405f9e363SConor Dooley default MCHP_CLK_MPFS 20505f9e363SConor Dooley help 20605f9e363SConor Dooley This driver supports peripheral reset for the Microchip PolarFire SoC 20705f9e363SConor Dooley 2085ecb0651SSibi Sankarconfig RESET_QCOM_AOSS 209e2d5e833SJohn Stultz tristate "Qcom AOSS Reset Driver" 2105ecb0651SSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 2115ecb0651SSibi Sankar help 2125ecb0651SSibi Sankar This enables the AOSS (always on subsystem) reset driver 2135ecb0651SSibi Sankar for Qualcomm SDM845 SoCs. Say Y if you want to control 2145ecb0651SSibi Sankar reset signals provided by AOSS for Modem, Venus, ADSP, 2155ecb0651SSibi Sankar GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 2165ecb0651SSibi Sankar 217eea2926bSSibi Sankarconfig RESET_QCOM_PDC 218eea2926bSSibi Sankar tristate "Qualcomm PDC Reset Driver" 219eea2926bSSibi Sankar depends on ARCH_QCOM || COMPILE_TEST 220eea2926bSSibi Sankar help 221eea2926bSSibi Sankar This enables the PDC (Power Domain Controller) reset driver 222eea2926bSSibi Sankar for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 223eea2926bSSibi Sankar to control reset signals provided by PDC for Modem, Compute, 224eea2926bSSibi Sankar Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 225eea2926bSSibi Sankar 226abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI 227abffc82aSNicolas Saenz Julienne tristate "Raspberry Pi 4 Firmware Reset Driver" 228abffc82aSNicolas Saenz Julienne depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 229abffc82aSNicolas Saenz Julienne default USB_XHCI_PCI 230abffc82aSNicolas Saenz Julienne help 231abffc82aSNicolas Saenz Julienne Raspberry Pi 4's co-processor controls some of the board's HW 232abffc82aSNicolas Saenz Julienne initialization process, but it's up to Linux to trigger it when 233abffc82aSNicolas Saenz Julienne relevant. This driver provides a reset controller capable of 234abffc82aSNicolas Saenz Julienne interfacing with RPi4's co-processor and model these firmware 235abffc82aSNicolas Saenz Julienne initialization routines as reset lines. 236abffc82aSNicolas Saenz Julienne 237bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL 238bee08559SBiju Das tristate "Renesas RZ/G2L USBPHY control driver" 2399fe7dd4eSLad Prabhakar depends on ARCH_RZG2L || COMPILE_TEST 240bee08559SBiju Das help 241bee08559SBiju Das Support for USBPHY Control found on RZ/G2L family. It mainly 242bee08559SBiju Das controls reset and power down of the USB/PHY. 243bee08559SBiju Das 244e3911d7fSLad Prabhakarconfig RESET_RZV2H_USB2PHY 245e3911d7fSLad Prabhakar tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 246e3911d7fSLad Prabhakar depends on ARCH_RENESAS || COMPILE_TEST 247e3911d7fSLad Prabhakar help 248e3911d7fSLad Prabhakar Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 249e3911d7fSLad Prabhakar (and similar SoCs). 250e3911d7fSLad Prabhakar 251c8ae9c2dSSudeep Hollaconfig RESET_SCMI 252c8ae9c2dSSudeep Holla tristate "Reset driver controlled via ARM SCMI interface" 253c8ae9c2dSSudeep Holla depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 254c8ae9c2dSSudeep Holla default ARM_SCMI_PROTOCOL 255c8ae9c2dSSudeep Holla help 256c8ae9c2dSSudeep Holla This driver provides support for reset signal/domains that are 257c8ae9c2dSSudeep Holla controlled by firmware that implements the SCMI interface. 258c8ae9c2dSSudeep Holla 259c8ae9c2dSSudeep Holla This driver uses SCMI Message Protocol to interact with the 260c8ae9c2dSSudeep Holla firmware controlling all the reset signals. 261c8ae9c2dSSudeep Holla 26281c22ad0SPhilipp Zabelconfig RESET_SIMPLE 26318d1909bSBen Dooks bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 264a6166a4dSChen Wang default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 265c4ada3caSBen Dooks depends on HAS_IOMEM 26681c22ad0SPhilipp Zabel help 26781c22ad0SPhilipp Zabel This enables a simple reset controller driver for reset lines that 26881c22ad0SPhilipp Zabel that can be asserted and deasserted by toggling bits in a contiguous, 26981c22ad0SPhilipp Zabel exclusive register space. 27081c22ad0SPhilipp Zabel 2711d7592f8SJoel Stanley Currently this driver supports: 2721d7592f8SJoel Stanley - Altera SoCFPGAs 2731d7592f8SJoel Stanley - ASPEED BMC SoCs 2745ac33eebSAndreas Färber - Bitmain BM1880 SoC 2753ab831e5SAndreas Färber - Realtek SoCs 2761d7592f8SJoel Stanley - RCC reset controller in STM32 MCUs 2771d7592f8SJoel Stanley - Allwinner SoCs 278e4d368e0SGreentime Hu - SiFive FU740 SoCs 279a6166a4dSChen Wang - Sophgo SoCs 2807e0e901dSPhilipp Zabel 281b3ca9888SDinh Nguyenconfig RESET_SOCFPGA 282225c13f0SKrzysztof Kozlowski bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 283225c13f0SKrzysztof Kozlowski default ARM && ARCH_INTEL_SOCFPGA 284b3ca9888SDinh Nguyen select RESET_SIMPLE 285b3ca9888SDinh Nguyen help 286b3ca9888SDinh Nguyen This enables the reset driver for the SoCFPGA ARMv7 platforms. This 287b3ca9888SDinh Nguyen driver gets initialized early during platform init calls. 288b3ca9888SDinh Nguyen 289c479d7cfSAlex Elderconfig RESET_SPACEMIT 290c479d7cfSAlex Elder tristate "SpacemiT reset driver" 291c479d7cfSAlex Elder depends on ARCH_SPACEMIT || COMPILE_TEST 292c479d7cfSAlex Elder select AUXILIARY_BUS 293c479d7cfSAlex Elder default ARCH_SPACEMIT 294c479d7cfSAlex Elder help 295c479d7cfSAlex Elder This enables the reset controller driver for SpacemiT SoCs, 296c479d7cfSAlex Elder including the K1. 297c479d7cfSAlex Elder 298dbf018beSQin Jianconfig RESET_SUNPLUS 299dbf018beSQin Jian bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 300dbf018beSQin Jian default ARCH_SUNPLUS 301dbf018beSQin Jian help 302dbf018beSQin Jian This enables the reset driver support for Sunplus SoCs. 303dbf018beSQin Jian The reset lines that can be asserted and deasserted by toggling bits 304dbf018beSQin Jian in a contiguous, exclusive register space. The register is HIWORD_MASKED, 305dbf018beSQin Jian which means each register holds 16 reset lines. 306dbf018beSQin Jian 3070ae08419SPhilipp Zabelconfig RESET_SUNXI 3080ae08419SPhilipp Zabel bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 3090ae08419SPhilipp Zabel default ARCH_SUNXI 310e13c205aSPhilipp Zabel select RESET_SIMPLE 3110ae08419SPhilipp Zabel help 3120ae08419SPhilipp Zabel This enables the reset driver for Allwinner SoCs. 3130ae08419SPhilipp Zabel 3144a653263SMichal Wilczynskiconfig RESET_TH1520 315e73bfb4cSDrew Fustini tristate "T-HEAD TH1520 reset controller" 3164a653263SMichal Wilczynski depends on ARCH_THEAD || COMPILE_TEST 3174a653263SMichal Wilczynski select REGMAP_MMIO 3184a653263SMichal Wilczynski help 3194a653263SMichal Wilczynski This driver provides support for the T-HEAD TH1520 SoC reset controller, 3204a653263SMichal Wilczynski which manages hardware reset lines for SoC components such as the GPU. 3214a653263SMichal Wilczynski Enable this option if you need to control hardware resets on TH1520-based 3224a653263SMichal Wilczynski systems. 3234a653263SMichal Wilczynski 32428df169bSAndrew F. Davisconfig RESET_TI_SCI 32528df169bSAndrew F. Davis tristate "TI System Control Interface (TI-SCI) reset driver" 32613678f3fSRandy Dunlap depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 32728df169bSAndrew F. Davis help 32828df169bSAndrew F. Davis This enables the reset driver support over TI System Control Interface 32928df169bSAndrew F. Davis available on some new TI's SoCs. If you wish to use reset resources 33028df169bSAndrew F. Davis managed by the TI System Controller, say Y here. Otherwise, say N. 33128df169bSAndrew F. Davis 332dd9bf863SSuman Annaconfig RESET_TI_SYSCON 333cc7c2bb1SAndrew F. Davis tristate "TI SYSCON Reset Driver" 334cc7c2bb1SAndrew F. Davis depends on HAS_IOMEM 335cc7c2bb1SAndrew F. Davis select MFD_SYSCON 336cc7c2bb1SAndrew F. Davis help 337cc7c2bb1SAndrew F. Davis This enables the reset driver support for TI devices with 338cc7c2bb1SAndrew F. Davis memory-mapped reset registers as part of a syscon device node. If 339cc7c2bb1SAndrew F. Davis you wish to use the reset framework for such memory-mapped devices, 340cc7c2bb1SAndrew F. Davis say Y here. Otherwise, say N. 341cc7c2bb1SAndrew F. Davis 3428a4e6154SMarco Felschconfig RESET_TI_TPS380X 3438a4e6154SMarco Felsch tristate "TI TPS380x Reset Driver" 3448a4e6154SMarco Felsch select GPIOLIB 3458a4e6154SMarco Felsch help 3468a4e6154SMarco Felsch This enables the reset driver support for TI TPS380x devices. If 3478a4e6154SMarco Felsch you wish to use the reset framework for such devices, say Y here. 3488a4e6154SMarco Felsch Otherwise, say N. 3498a4e6154SMarco Felsch 3505cd3921dSRobert Markoconfig RESET_TN48M_CPLD 3515cd3921dSRobert Marko tristate "Delta Networks TN48M switch CPLD reset controller" 3525cd3921dSRobert Marko depends on MFD_TN48M_CPLD || COMPILE_TEST 3535cd3921dSRobert Marko default MFD_TN48M_CPLD 3545cd3921dSRobert Marko help 3555cd3921dSRobert Marko This enables the reset controller driver for the Delta TN48M CPLD. 3565cd3921dSRobert Marko It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 3575cd3921dSRobert Marko switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 3585cd3921dSRobert Marko Microchip PD69200 PoE PSE controller. 3595cd3921dSRobert Marko 3605cd3921dSRobert Marko This driver can also be built as a module. If so, the module will be 3615cd3921dSRobert Marko called reset-tn48m. 3625cd3921dSRobert Marko 36354e991b5SMasahiro Yamadaconfig RESET_UNIPHIER 36454e991b5SMasahiro Yamada tristate "Reset controller driver for UniPhier SoCs" 36554e991b5SMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 36654e991b5SMasahiro Yamada depends on OF && MFD_SYSCON 36754e991b5SMasahiro Yamada default ARCH_UNIPHIER 36854e991b5SMasahiro Yamada help 36954e991b5SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 37054e991b5SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 37154e991b5SMasahiro Yamada block, Media I/O block, Peripheral Block. 37254e991b5SMasahiro Yamada 3733eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE 3743eb8f765SKunihiko Hayashi tristate "Reset driver in glue layer for UniPhier SoCs" 375499fef09SKunihiko Hayashi depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 376499fef09SKunihiko Hayashi default ARCH_UNIPHIER 377499fef09SKunihiko Hayashi select RESET_SIMPLE 378499fef09SKunihiko Hayashi help 3793eb8f765SKunihiko Hayashi Support for peripheral core reset included in its own glue layer 3803eb8f765SKunihiko Hayashi on UniPhier SoCs. Say Y if you want to control reset signals 3813eb8f765SKunihiko Hayashi provided by the glue layer. 382499fef09SKunihiko Hayashi 3836f51b860SPhilipp Zabelconfig RESET_ZYNQ 3846f51b860SPhilipp Zabel bool "ZYNQ Reset Driver" if COMPILE_TEST 3856f51b860SPhilipp Zabel default ARCH_ZYNQ 3866f51b860SPhilipp Zabel help 3876f51b860SPhilipp Zabel This enables the reset controller driver for Xilinx Zynq SoCs. 3886f51b860SPhilipp Zabel 3894f6a43adSPhilipp Zabelconfig RESET_ZYNQMP 3904f6a43adSPhilipp Zabel bool "ZYNQMP Reset Driver" if COMPILE_TEST 3914f6a43adSPhilipp Zabel default ARCH_ZYNQMP 3924f6a43adSPhilipp Zabel help 3934f6a43adSPhilipp Zabel This enables the reset controller driver for Xilinx ZynqMP SoCs. 3944f6a43adSPhilipp Zabel 3952c138ee3SJerome Brunetsource "drivers/reset/amlogic/Kconfig" 39669bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig" 397e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig" 398f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig" 399dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig" 400998cd463SMasahiro Yamada 401998cd463SMasahiro Yamadaendif 402