xref: /linux/drivers/reset/Kconfig (revision 297d9111e9fcf47dd1dcc6f79bba915f35378d01)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER
361fc4131SPhilipp Zabel	bool
461fc4131SPhilipp Zabel
561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER
661fc4131SPhilipp Zabel	bool "Reset Controller Support"
761fc4131SPhilipp Zabel	default y if ARCH_HAS_RESET_CONTROLLER
861fc4131SPhilipp Zabel	help
961fc4131SPhilipp Zabel	  Generic Reset Controller support.
1061fc4131SPhilipp Zabel
1161fc4131SPhilipp Zabel	  This framework is designed to abstract reset handling of devices
1261fc4131SPhilipp Zabel	  via GPIOs or SoC-internal reset controller modules.
1361fc4131SPhilipp Zabel
1461fc4131SPhilipp Zabel	  If unsure, say no.
15e5d76075SStephen Gallimore
16998cd463SMasahiro Yamadaif RESET_CONTROLLER
17998cd463SMasahiro Yamada
1862700682SThor Thayerconfig RESET_A10SR
1962700682SThor Thayer	tristate "Altera Arria10 System Resource Reset"
20af19f193SPhilipp Zabel	depends on MFD_ALTERA_A10SR || COMPILE_TEST
2162700682SThor Thayer	help
2262700682SThor Thayer	  This option enables support for the external reset functions for
2362700682SThor Thayer	  peripheral PHYs on the Altera Arria10 System Resource Chip.
2462700682SThor Thayer
25e27b4a6eSPhilipp Zabelconfig RESET_ATH79
26e27b4a6eSPhilipp Zabel	bool "AR71xx Reset Driver" if COMPILE_TEST
27e27b4a6eSPhilipp Zabel	default ATH79
28e27b4a6eSPhilipp Zabel	help
29e27b4a6eSPhilipp Zabel	  This enables the ATH79 reset controller driver that supports the
30e27b4a6eSPhilipp Zabel	  AR71xx SoC reset controller.
31e27b4a6eSPhilipp Zabel
3237634923SEugeniy Paltsevconfig RESET_AXS10X
3337634923SEugeniy Paltsev	bool "AXS10x Reset Driver" if COMPILE_TEST
3437634923SEugeniy Paltsev	default ARC_PLAT_AXS10X
3537634923SEugeniy Paltsev	help
3637634923SEugeniy Paltsev	  This enables the reset controller driver for AXS10x.
3737634923SEugeniy Paltsev
38aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345
39aac02543SÁlvaro Fernández Rojas	bool "BCM6345 Reset Controller"
40aac02543SÁlvaro Fernández Rojas	depends on BMIPS_GENERIC || COMPILE_TEST
41aac02543SÁlvaro Fernández Rojas	default BMIPS_GENERIC
42aac02543SÁlvaro Fernández Rojas	help
43aac02543SÁlvaro Fernández Rojas	  This enables the reset controller driver for BCM6345 SoCs.
44aac02543SÁlvaro Fernández Rojas
4570d467eaSPhilipp Zabelconfig RESET_BERLIN
465e787cdfSJisheng Zhang	tristate "Berlin Reset Driver"
475e787cdfSJisheng Zhang	depends on ARCH_BERLIN || COMPILE_TEST
485e787cdfSJisheng Zhang	default m if ARCH_BERLIN
4970d467eaSPhilipp Zabel	help
5070d467eaSPhilipp Zabel	  This enables the reset controller driver for Marvell Berlin SoCs.
5170d467eaSPhilipp Zabel
5277750bc0SFlorian Fainelliconfig RESET_BRCMSTB
5377750bc0SFlorian Fainelli	tristate "Broadcom STB reset controller"
5477750bc0SFlorian Fainelli	depends on ARCH_BRCMSTB || COMPILE_TEST
5577750bc0SFlorian Fainelli	default ARCH_BRCMSTB
5677750bc0SFlorian Fainelli	help
5777750bc0SFlorian Fainelli	  This enables the reset controller driver for Broadcom STB SoCs using
5877750bc0SFlorian Fainelli	  a SUN_TOP_CTRL_SW_INIT style controller.
5977750bc0SFlorian Fainelli
604cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL
615694ca29SFlorian Fainelli	tristate "Broadcom STB RESCAL reset controller"
627fbcc535SBrendan Higgins	depends on HAS_IOMEM
6342f6a76fSGeert Uytterhoeven	depends on ARCH_BRCMSTB || COMPILE_TEST
6442f6a76fSGeert Uytterhoeven	default ARCH_BRCMSTB
654cf176e5SJim Quinlan	help
664cf176e5SJim Quinlan	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
674cf176e5SJim Quinlan	  BCM7216.
684cf176e5SJim Quinlan
69487b1b32SThéo Lebrunconfig RESET_EYEQ
70487b1b32SThéo Lebrun	bool "Mobileye EyeQ reset controller"
71487b1b32SThéo Lebrun	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
72487b1b32SThéo Lebrun	select AUXILIARY_BUS
73487b1b32SThéo Lebrun	default MACH_EYEQ5 || MACH_EYEQ6H
74487b1b32SThéo Lebrun	help
75487b1b32SThéo Lebrun	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
76487b1b32SThéo Lebrun	  and EyeQ6H SoCs.
77487b1b32SThéo Lebrun
78487b1b32SThéo Lebrun	  It has one or more domains, with a varying number of resets in each.
79487b1b32SThéo Lebrun	  Registers are located in a shared register region called OLB. EyeQ6H
80487b1b32SThéo Lebrun	  has multiple reset instances.
81487b1b32SThéo Lebrun
82cee544a4SKrzysztof Kozlowskiconfig RESET_GPIO
83cee544a4SKrzysztof Kozlowski	tristate "GPIO reset controller"
8401f6a84cSMark Brown	depends on GPIOLIB
85cee544a4SKrzysztof Kozlowski	help
86cee544a4SKrzysztof Kozlowski	  This enables a generic reset controller for resets attached via
87cee544a4SKrzysztof Kozlowski	  GPIOs.  Typically for OF platforms this driver expects "reset-gpios"
88cee544a4SKrzysztof Kozlowski	  property.
89cee544a4SKrzysztof Kozlowski
90cee544a4SKrzysztof Kozlowski	  If compiled as module, it will be called reset-gpio.
91cee544a4SKrzysztof Kozlowski
9213541226SVineet Guptaconfig RESET_HSDK
9313541226SVineet Gupta	bool "Synopsys HSDK Reset Driver"
942d48a237SThomas Meyer	depends on HAS_IOMEM
95544e3bf4SGeert Uytterhoeven	depends on ARC_SOC_HSDK || COMPILE_TEST
96e0be864fSEugeniy Paltsev	help
9713541226SVineet Gupta	  This enables the reset controller driver for HSDK board.
98e0be864fSEugeniy Paltsev
996b64fde5SFrank Liconfig RESET_IMX_SCU
1006b64fde5SFrank Li	tristate "i.MX8Q Reset Driver"
1016b64fde5SFrank Li	depends on IMX_SCU && HAVE_ARM_SMCCC
1026b64fde5SFrank Li	depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
1036b64fde5SFrank Li	help
1046b64fde5SFrank Li          This enables the reset controller driver for i.MX8QM/i.MX8QXP
1056b64fde5SFrank Li
106abf97755SAndrey Smirnovconfig RESET_IMX7
107a442abbbSAnson Huang	tristate "i.MX7/8 Reset Driver"
1088fa56620SMasahiro Yamada	depends on HAS_IOMEM
109a442abbbSAnson Huang	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
110a442abbbSAnson Huang	default y if SOC_IMX7D
111abf97755SAndrey Smirnov	select MFD_SYSCON
112abf97755SAndrey Smirnov	help
113abf97755SAndrey Smirnov	  This enables the reset controller driver for i.MX7 SoCs.
114abf97755SAndrey Smirnov
115fe125601SShengjiu Wangconfig RESET_IMX8MP_AUDIOMIX
116fe125601SShengjiu Wang	tristate "i.MX8MP AudioMix Reset Driver"
117eb5d88b1SGeert Uytterhoeven	depends on ARCH_MXC || COMPILE_TEST
118fe125601SShengjiu Wang	select AUXILIARY_BUS
119fe125601SShengjiu Wang	default CLK_IMX8MP
120fe125601SShengjiu Wang	help
121fe125601SShengjiu Wang	  This enables the reset controller driver for i.MX8MP AudioMix
122fe125601SShengjiu Wang
123c9aef213SDilip Kotaconfig RESET_INTEL_GW
124c9aef213SDilip Kota	bool "Intel Reset Controller Driver"
1256ab9d621SGeert Uytterhoeven	depends on X86 || COMPILE_TEST
126b460e0a9SBrendan Higgins	depends on OF && HAS_IOMEM
127c9aef213SDilip Kota	select REGMAP_MMIO
128c9aef213SDilip Kota	help
129c9aef213SDilip Kota	  This enables the reset controller driver for Intel Gateway SoCs.
130c9aef213SDilip Kota	  Say Y to control the reset signals provided by reset controller.
131c9aef213SDilip Kota	  Otherwise, say N.
132c9aef213SDilip Kota
1335a2308daSDamien Le Moalconfig RESET_K210
1345a2308daSDamien Le Moal	bool "Reset controller driver for Canaan Kendryte K210 SoC"
13568f41105SYangyu Chen	depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
1365a2308daSDamien Le Moal	select MFD_SYSCON
13768f41105SYangyu Chen	default SOC_CANAAN_K210
1385a2308daSDamien Le Moal	help
1395a2308daSDamien Le Moal	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
1405a2308daSDamien Le Moal	  Say Y if you want to control reset signals provided by this
1415a2308daSDamien Le Moal	  controller.
1425a2308daSDamien Le Moal
14379797b6fSMartin Blumenstinglconfig RESET_LANTIQ
14479797b6fSMartin Blumenstingl	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
14579797b6fSMartin Blumenstingl	default SOC_TYPE_XWAY
14679797b6fSMartin Blumenstingl	help
14779797b6fSMartin Blumenstingl	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
14879797b6fSMartin Blumenstingl
149cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX
150cd7f4b81SPhilipp Zabel	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
151cd7f4b81SPhilipp Zabel	default ARCH_LPC18XX
152cd7f4b81SPhilipp Zabel	help
153cd7f4b81SPhilipp Zabel	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
154cd7f4b81SPhilipp Zabel
155453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5
156996737efSClément Léger	tristate "Microchip Sparx5 reset driver"
157eba0deddSHerve Codina	depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
158453ed428SSteen Hegelund	default y if SPARX5_SWITCH
159453ed428SSteen Hegelund	select MFD_SYSCON
160453ed428SSteen Hegelund	help
161453ed428SSteen Hegelund	  This driver supports switch core reset for the Microchip Sparx5 SoC.
162453ed428SSteen Hegelund
1639c81b2ccSTomer Maimonconfig RESET_NPCM
1649c81b2ccSTomer Maimon	bool "NPCM BMC Reset Driver" if COMPILE_TEST
1659c81b2ccSTomer Maimon	default ARCH_NPCM
16622823157STomer Maimon	select AUXILIARY_BUS
1679c81b2ccSTomer Maimon	help
1689c81b2ccSTomer Maimon	  This enables the reset controller driver for Nuvoton NPCM
1699c81b2ccSTomer Maimon	  BMC SoCs.
1709c81b2ccSTomer Maimon
171e4bb55d6SJacky Huangconfig RESET_NUVOTON_MA35D1
172aead1076SGeert Uytterhoeven	bool "Nuvoton MA35D1 Reset Driver"
173aead1076SGeert Uytterhoeven	depends on ARCH_MA35 || COMPILE_TEST
174aead1076SGeert Uytterhoeven	default ARCH_MA35
175e4bb55d6SJacky Huang	help
176e4bb55d6SJacky Huang	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
177e4bb55d6SJacky Huang
178fab3f730SPhilipp Zabelconfig RESET_PISTACHIO
1794af16070SGeert Uytterhoeven	bool "Pistachio Reset Driver"
1804af16070SGeert Uytterhoeven	depends on MIPS || COMPILE_TEST
181fab3f730SPhilipp Zabel	help
182fab3f730SPhilipp Zabel	  This enables the reset driver for ImgTec Pistachio SoCs.
183fab3f730SPhilipp Zabel
18405f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC
18505f9e363SConor Dooley	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
186afb39e2bSPhilipp Zabel	depends on MCHP_CLK_MPFS
187afb39e2bSPhilipp Zabel	select AUXILIARY_BUS
18805f9e363SConor Dooley	default MCHP_CLK_MPFS
18905f9e363SConor Dooley	help
19005f9e363SConor Dooley	  This driver supports peripheral reset for the Microchip PolarFire SoC
19105f9e363SConor Dooley
1925ecb0651SSibi Sankarconfig RESET_QCOM_AOSS
193e2d5e833SJohn Stultz	tristate "Qcom AOSS Reset Driver"
1945ecb0651SSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
1955ecb0651SSibi Sankar	help
1965ecb0651SSibi Sankar	  This enables the AOSS (always on subsystem) reset driver
1975ecb0651SSibi Sankar	  for Qualcomm SDM845 SoCs. Say Y if you want to control
1985ecb0651SSibi Sankar	  reset signals provided by AOSS for Modem, Venus, ADSP,
1995ecb0651SSibi Sankar	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
2005ecb0651SSibi Sankar
201eea2926bSSibi Sankarconfig RESET_QCOM_PDC
202eea2926bSSibi Sankar	tristate "Qualcomm PDC Reset Driver"
203eea2926bSSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
204eea2926bSSibi Sankar	help
205eea2926bSSibi Sankar	  This enables the PDC (Power Domain Controller) reset driver
206eea2926bSSibi Sankar	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
207eea2926bSSibi Sankar	  to control reset signals provided by PDC for Modem, Compute,
208eea2926bSSibi Sankar	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
209eea2926bSSibi Sankar
210abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI
211abffc82aSNicolas Saenz Julienne	tristate "Raspberry Pi 4 Firmware Reset Driver"
212abffc82aSNicolas Saenz Julienne	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
213abffc82aSNicolas Saenz Julienne	default USB_XHCI_PCI
214abffc82aSNicolas Saenz Julienne	help
215abffc82aSNicolas Saenz Julienne	  Raspberry Pi 4's co-processor controls some of the board's HW
216abffc82aSNicolas Saenz Julienne	  initialization process, but it's up to Linux to trigger it when
217abffc82aSNicolas Saenz Julienne	  relevant. This driver provides a reset controller capable of
218abffc82aSNicolas Saenz Julienne	  interfacing with RPi4's co-processor and model these firmware
219abffc82aSNicolas Saenz Julienne	  initialization routines as reset lines.
220abffc82aSNicolas Saenz Julienne
221bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL
222bee08559SBiju Das	tristate "Renesas RZ/G2L USBPHY control driver"
2239fe7dd4eSLad Prabhakar	depends on ARCH_RZG2L || COMPILE_TEST
224bee08559SBiju Das	help
225bee08559SBiju Das	  Support for USBPHY Control found on RZ/G2L family. It mainly
226bee08559SBiju Das	  controls reset and power down of the USB/PHY.
227bee08559SBiju Das
228*e3911d7fSLad Prabhakarconfig RESET_RZV2H_USB2PHY
229*e3911d7fSLad Prabhakar	tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
230*e3911d7fSLad Prabhakar	depends on ARCH_RENESAS || COMPILE_TEST
231*e3911d7fSLad Prabhakar	help
232*e3911d7fSLad Prabhakar	  Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
233*e3911d7fSLad Prabhakar	  (and similar SoCs).
234*e3911d7fSLad Prabhakar
235c8ae9c2dSSudeep Hollaconfig RESET_SCMI
236c8ae9c2dSSudeep Holla	tristate "Reset driver controlled via ARM SCMI interface"
237c8ae9c2dSSudeep Holla	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
238c8ae9c2dSSudeep Holla	default ARM_SCMI_PROTOCOL
239c8ae9c2dSSudeep Holla	help
240c8ae9c2dSSudeep Holla	  This driver provides support for reset signal/domains that are
241c8ae9c2dSSudeep Holla	  controlled by firmware that implements the SCMI interface.
242c8ae9c2dSSudeep Holla
243c8ae9c2dSSudeep Holla	  This driver uses SCMI Message Protocol to interact with the
244c8ae9c2dSSudeep Holla	  firmware controlling all the reset signals.
245c8ae9c2dSSudeep Holla
24681c22ad0SPhilipp Zabelconfig RESET_SIMPLE
24718d1909bSBen Dooks	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
248a6166a4dSChen Wang	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
249c4ada3caSBen Dooks	depends on HAS_IOMEM
25081c22ad0SPhilipp Zabel	help
25181c22ad0SPhilipp Zabel	  This enables a simple reset controller driver for reset lines that
25281c22ad0SPhilipp Zabel	  that can be asserted and deasserted by toggling bits in a contiguous,
25381c22ad0SPhilipp Zabel	  exclusive register space.
25481c22ad0SPhilipp Zabel
2551d7592f8SJoel Stanley	  Currently this driver supports:
2561d7592f8SJoel Stanley	   - Altera SoCFPGAs
2571d7592f8SJoel Stanley	   - ASPEED BMC SoCs
2585ac33eebSAndreas Färber	   - Bitmain BM1880 SoC
2593ab831e5SAndreas Färber	   - Realtek SoCs
2601d7592f8SJoel Stanley	   - RCC reset controller in STM32 MCUs
2611d7592f8SJoel Stanley	   - Allwinner SoCs
262e4d368e0SGreentime Hu	   - SiFive FU740 SoCs
263a6166a4dSChen Wang	   - Sophgo SoCs
2647e0e901dSPhilipp Zabel
265b3ca9888SDinh Nguyenconfig RESET_SOCFPGA
266225c13f0SKrzysztof Kozlowski	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
267225c13f0SKrzysztof Kozlowski	default ARM && ARCH_INTEL_SOCFPGA
268b3ca9888SDinh Nguyen	select RESET_SIMPLE
269b3ca9888SDinh Nguyen	help
270b3ca9888SDinh Nguyen	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
271b3ca9888SDinh Nguyen	  driver gets initialized early during platform init calls.
272b3ca9888SDinh Nguyen
273dbf018beSQin Jianconfig RESET_SUNPLUS
274dbf018beSQin Jian	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
275dbf018beSQin Jian	default ARCH_SUNPLUS
276dbf018beSQin Jian	help
277dbf018beSQin Jian	  This enables the reset driver support for Sunplus SoCs.
278dbf018beSQin Jian	  The reset lines that can be asserted and deasserted by toggling bits
279dbf018beSQin Jian	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
280dbf018beSQin Jian	  which means each register holds 16 reset lines.
281dbf018beSQin Jian
2820ae08419SPhilipp Zabelconfig RESET_SUNXI
2830ae08419SPhilipp Zabel	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
2840ae08419SPhilipp Zabel	default ARCH_SUNXI
285e13c205aSPhilipp Zabel	select RESET_SIMPLE
2860ae08419SPhilipp Zabel	help
2870ae08419SPhilipp Zabel	  This enables the reset driver for Allwinner SoCs.
2880ae08419SPhilipp Zabel
2894a653263SMichal Wilczynskiconfig RESET_TH1520
2904a653263SMichal Wilczynski	tristate "T-HEAD 1520 reset controller"
2914a653263SMichal Wilczynski	depends on ARCH_THEAD || COMPILE_TEST
2924a653263SMichal Wilczynski	select REGMAP_MMIO
2934a653263SMichal Wilczynski	help
2944a653263SMichal Wilczynski	  This driver provides support for the T-HEAD TH1520 SoC reset controller,
2954a653263SMichal Wilczynski	  which manages hardware reset lines for SoC components such as the GPU.
2964a653263SMichal Wilczynski	  Enable this option if you need to control hardware resets on TH1520-based
2974a653263SMichal Wilczynski	  systems.
2984a653263SMichal Wilczynski
29928df169bSAndrew F. Davisconfig RESET_TI_SCI
30028df169bSAndrew F. Davis	tristate "TI System Control Interface (TI-SCI) reset driver"
30113678f3fSRandy Dunlap	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
30228df169bSAndrew F. Davis	help
30328df169bSAndrew F. Davis	  This enables the reset driver support over TI System Control Interface
30428df169bSAndrew F. Davis	  available on some new TI's SoCs. If you wish to use reset resources
30528df169bSAndrew F. Davis	  managed by the TI System Controller, say Y here. Otherwise, say N.
30628df169bSAndrew F. Davis
307dd9bf863SSuman Annaconfig RESET_TI_SYSCON
308cc7c2bb1SAndrew F. Davis	tristate "TI SYSCON Reset Driver"
309cc7c2bb1SAndrew F. Davis	depends on HAS_IOMEM
310cc7c2bb1SAndrew F. Davis	select MFD_SYSCON
311cc7c2bb1SAndrew F. Davis	help
312cc7c2bb1SAndrew F. Davis	  This enables the reset driver support for TI devices with
313cc7c2bb1SAndrew F. Davis	  memory-mapped reset registers as part of a syscon device node. If
314cc7c2bb1SAndrew F. Davis	  you wish to use the reset framework for such memory-mapped devices,
315cc7c2bb1SAndrew F. Davis	  say Y here. Otherwise, say N.
316cc7c2bb1SAndrew F. Davis
3178a4e6154SMarco Felschconfig RESET_TI_TPS380X
3188a4e6154SMarco Felsch	tristate "TI TPS380x Reset Driver"
3198a4e6154SMarco Felsch	select GPIOLIB
3208a4e6154SMarco Felsch	help
3218a4e6154SMarco Felsch	  This enables the reset driver support for TI TPS380x devices. If
3228a4e6154SMarco Felsch	  you wish to use the reset framework for such devices, say Y here.
3238a4e6154SMarco Felsch	  Otherwise, say N.
3248a4e6154SMarco Felsch
3255cd3921dSRobert Markoconfig RESET_TN48M_CPLD
3265cd3921dSRobert Marko	tristate "Delta Networks TN48M switch CPLD reset controller"
3275cd3921dSRobert Marko	depends on MFD_TN48M_CPLD || COMPILE_TEST
3285cd3921dSRobert Marko	default MFD_TN48M_CPLD
3295cd3921dSRobert Marko	help
3305cd3921dSRobert Marko	  This enables the reset controller driver for the Delta TN48M CPLD.
3315cd3921dSRobert Marko	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
3325cd3921dSRobert Marko	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
3335cd3921dSRobert Marko	  Microchip PD69200 PoE PSE controller.
3345cd3921dSRobert Marko
3355cd3921dSRobert Marko	  This driver can also be built as a module. If so, the module will be
3365cd3921dSRobert Marko	  called reset-tn48m.
3375cd3921dSRobert Marko
33854e991b5SMasahiro Yamadaconfig RESET_UNIPHIER
33954e991b5SMasahiro Yamada	tristate "Reset controller driver for UniPhier SoCs"
34054e991b5SMasahiro Yamada	depends on ARCH_UNIPHIER || COMPILE_TEST
34154e991b5SMasahiro Yamada	depends on OF && MFD_SYSCON
34254e991b5SMasahiro Yamada	default ARCH_UNIPHIER
34354e991b5SMasahiro Yamada	help
34454e991b5SMasahiro Yamada	  Support for reset controllers on UniPhier SoCs.
34554e991b5SMasahiro Yamada	  Say Y if you want to control reset signals provided by System Control
34654e991b5SMasahiro Yamada	  block, Media I/O block, Peripheral Block.
34754e991b5SMasahiro Yamada
3483eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE
3493eb8f765SKunihiko Hayashi	tristate "Reset driver in glue layer for UniPhier SoCs"
350499fef09SKunihiko Hayashi	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
351499fef09SKunihiko Hayashi	default ARCH_UNIPHIER
352499fef09SKunihiko Hayashi	select RESET_SIMPLE
353499fef09SKunihiko Hayashi	help
3543eb8f765SKunihiko Hayashi	  Support for peripheral core reset included in its own glue layer
3553eb8f765SKunihiko Hayashi	  on UniPhier SoCs. Say Y if you want to control reset signals
3563eb8f765SKunihiko Hayashi	  provided by the glue layer.
357499fef09SKunihiko Hayashi
3586f51b860SPhilipp Zabelconfig RESET_ZYNQ
3596f51b860SPhilipp Zabel	bool "ZYNQ Reset Driver" if COMPILE_TEST
3606f51b860SPhilipp Zabel	default ARCH_ZYNQ
3616f51b860SPhilipp Zabel	help
3626f51b860SPhilipp Zabel	  This enables the reset controller driver for Xilinx Zynq SoCs.
3636f51b860SPhilipp Zabel
3644f6a43adSPhilipp Zabelconfig RESET_ZYNQMP
3654f6a43adSPhilipp Zabel	bool "ZYNQMP Reset Driver" if COMPILE_TEST
3664f6a43adSPhilipp Zabel	default ARCH_ZYNQMP
3674f6a43adSPhilipp Zabel	help
3684f6a43adSPhilipp Zabel	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
3694f6a43adSPhilipp Zabel
3702c138ee3SJerome Brunetsource "drivers/reset/amlogic/Kconfig"
37169bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig"
372e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig"
373f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig"
374dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig"
375998cd463SMasahiro Yamada
376998cd463SMasahiro Yamadaendif
377