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/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/linux/arch/powerpc/kvm/
H A Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/drivers/soc/mediatek/
H A Dmt8186-mmsys.h7 #define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
8 #define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
9 #define MT8186_DPI_RGB888_SDR_CON 0
14 #define MT8186_MMSYS_OVL_CON 0xF04
15 #define MT8186_MMSYS_OVL0_CON_MASK 0x3
16 #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
17 #define MT8186_OVL0_GO_BLEND BIT(0)
21 #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
22 #define MT8186_RDMA0_SOUT_SEL_MASK 0xF
23 #define MT8186_RDMA0_SOUT_TO_DSI0 (0)
[all …]
/linux/arch/powerpc/include/asm/
H A Dkvm_asm.h27 #define BOOKE_INTERRUPT_CRITICAL 0
69 #define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
70 #define BOOK3S_INTERRUPT_MACHINE_CHECK 0x200
71 #define BOOK3S_INTERRUPT_DATA_STORAGE 0x300
72 #define BOOK3S_INTERRUPT_DATA_SEGMENT 0x380
73 #define BOOK3S_INTERRUPT_INST_STORAGE 0x400
74 #define BOOK3S_INTERRUPT_INST_SEGMENT 0x480
75 #define BOOK3S_INTERRUPT_EXTERNAL 0x500
76 #define BOOK3S_INTERRUPT_EXTERNAL_HV 0x502
77 #define BOOK3S_INTERRUPT_ALIGNMENT 0x600
[all …]
H A Dinterrupt.h6 #define INTERRUPT_CRITICAL_INPUT 0x100
9 #define INTERRUPT_DEBUG 0xd00
11 #define INTERRUPT_PERFMON 0x260
12 #define INTERRUPT_DOORBELL 0x280
16 #define INTERRUPT_MACHINE_CHECK 0x200
19 #define INTERRUPT_SYSTEM_RESET 0x100
22 #define INTERRUPT_DATA_SEGMENT 0x380
23 #define INTERRUPT_INST_SEGMENT 0x480
24 #define INTERRUPT_TRACE 0xd00
25 #define INTERRUPT_H_DATA_STORAGE 0xe00
[all …]
/linux/include/linux/irqchip/
H A Darm-gic.h10 #define GIC_CPU_CTRL 0x00
11 #define GIC_CPU_PRIMASK 0x04
12 #define GIC_CPU_BINPOINT 0x08
13 #define GIC_CPU_INTACK 0x0c
14 #define GIC_CPU_EOI 0x10
15 #define GIC_CPU_RUNNINGPRI 0x14
16 #define GIC_CPU_HIGHPRI 0x18
17 #define GIC_CPU_ALIAS_BINPOINT 0x1c
18 #define GIC_CPU_ACTIVEPRIO 0xd0
19 #define GIC_CPU_IDENT 0xfc
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sa8775p.yaml91 reg = <0x0 0x01c00000 0x0 0x3000>,
92 <0x0 0x40000000 0x0 0xf20>,
93 <0x0 0x40000f20 0x0 0xa8>,
94 <0x0 0x40001000 0x0 0x4000>,
95 <0x0 0x40100000 0x0 0x100000>,
96 <0x0 0x01c03000 0x0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
[all …]
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x05_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0xf80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0xe80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0xf00 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0xf20 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0xc00 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x3ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x3ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
H A Dhw_host1x04_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0xf80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0xe80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0xf00 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0xf20 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0xc00 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x3ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x3ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_regs.h106 #define GAUDI_ECC_MEM_SEL_OFFSET 0xF18
107 #define GAUDI_ECC_ADDRESS_OFFSET 0xF1C
108 #define GAUDI_ECC_SYNDROME_OFFSET 0xF20
109 #define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28
112 #define GAUDI_ECC_SERR0_OFFSET 0xF30
113 #define GAUDI_ECC_DERR0_OFFSET 0xF40
115 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000
116 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000
117 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800
118 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
26 #define MTK_WED_REV_ID 0x004
28 #define MTK_WED_RESET 0x008
29 #define MTK_WED_RESET_TX_BM BIT(0)
48 #define MTK_WED_CTRL 0x00c
49 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
75 #define MTK_WED_EXT_INT_STATUS 0x020
76 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
103 #define MTK_WED_EXT_INT_MASK 0x028
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/linux/arch/powerpc/kernel/
H A Dexceptions-64e.S39 #define SPECIAL_EXC_SRR0 0
83 lwz r12,0(r11)
119 li r10,0
145 lwz r12,0(r11)
164 PPC_TLBILX_ALL(0,R0)
200 stdcx. r0,0,r1 /* to clear the reservation */
228 REST_GPR(0, r1)
264 cmpdi cr1,r1,0; /* check if SP makes sense */ \
368 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
385 ZEROIZE_GPR(0); \
[all …]
H A Dexceptions-64s.S130 IHSRR=0
133 IHSRR_IF_HVMODE=0
142 IISIDE=0
148 ICFAR_IF_HVMODE=0
151 IDAR=0
154 IDSISR=0
160 IREALMODE_COMMON=0
163 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
167 IMASK=0
170 IKVM_REAL=0
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0xc00)),
32 .id = 0,
41 [0] = {
43 .start = 0x04470000,
44 .end = 0x04470017,
48 .start = evt2irq(0xe00),
49 .end = evt2irq(0xe60),
56 .id = 0, /* "i2c0" clock */
66 [0] = {
[all …]
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
H A Dsetup-sh7343.c24 DEFINE_RES_MEM(0xffe00000, 0x100),
25 DEFINE_RES_IRQ(evt2irq(0xc00)),
30 .id = 0,
44 DEFINE_RES_MEM(0xffe10000, 0x100),
45 DEFINE_RES_IRQ(evt2irq(0xc20)),
64 DEFINE_RES_MEM(0xffe20000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0xc40)),
84 DEFINE_RES_MEM(0xffe30000, 0x100),
85 DEFINE_RES_IRQ(evt2irq(0xc60)),
99 [0] = {
[all …]
H A Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]
H A Dsetup-sh7780.c25 DEFINE_RES_MEM(0xffe00000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
31 .id = 0,
46 DEFINE_RES_MEM(0xffe10000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0xb80)),
65 DEFINE_RES_MEM(0xffd80000, 0x30),
66 DEFINE_RES_IRQ(evt2irq(0x580)),
67 DEFINE_RES_IRQ(evt2irq(0x5a0)),
68 DEFINE_RES_IRQ(evt2irq(0x5c0)),
73 .id = 0,
[all …]
H A Dsetup-sh7770.c22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
[all …]
H A Dsetup-sh7723.c33 DEFINE_RES_MEM(0xffe00000, 0x100),
34 DEFINE_RES_IRQ(evt2irq(0xc00)),
39 .id = 0,
54 DEFINE_RES_MEM(0xffe10000, 0x100),
55 DEFINE_RES_IRQ(evt2irq(0xc20)),
75 DEFINE_RES_MEM(0xffe20000, 0x100),
76 DEFINE_RES_IRQ(evt2irq(0xc40)),
95 DEFINE_RES_MEM(0xa4e30000, 0x100),
96 DEFINE_RES_IRQ(evt2irq(0x900)),
115 DEFINE_RES_MEM(0xa4e40000, 0x100),
[all …]
H A Dsetup-sh7785.c27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
[all …]
/linux/drivers/net/wireless/ath/wcn36xx/
H A Ddxe.h31 #define WCN36XX_DXE_MEM_REG 0
33 #define WCN36XX_CCU_DXE_INT_SELECT_RIVA 0x310
34 #define WCN36XX_CCU_DXE_INT_SELECT_PRONTO 0x10dc
37 #define WCN36xx_DXE_CTRL_VLD BIT(0)
81 #define WCN36xx_DXE_XTYPE_H2H (0)
138 #define WCN36XX_DXE_WQ_TX_L(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17)
139 #define WCN36XX_DXE_WQ_TX_H(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17)
140 #define WCN36XX_DXE_WQ_RX_L 0xB
141 #define WCN36XX_DXE_WQ_RX_H 0x4
144 #define WCN36xx_DXE_CH_CTRL_EN BIT(0)
[all …]
/linux/sound/pci/lola/
H A Dlola.h17 #define LOLA_BAR0_GCAP 0x00
18 #define LOLA_BAR0_VMIN 0x02
19 #define LOLA_BAR0_VMAJ 0x03
20 #define LOLA_BAR0_OUTPAY 0x04
21 #define LOLA_BAR0_INPAY 0x06
22 #define LOLA_BAR0_GCTL 0x08
23 #define LOLA_BAR0_WAKEEN 0x0c
24 #define LOLA_BAR0_STATESTS 0x0e
25 #define LOLA_BAR0_GSTS 0x10
26 #define LOLA_BAR0_OUTSTRMPAY 0x18
[all …]

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