Lines Matching +full:0 +full:xf20
27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
112 DEFINE_RES_IRQ(evt2irq(0x9c0)),
132 DEFINE_RES_MEM(0xffef0000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0x9e0)),
151 DEFINE_RES_MEM(0xffd80000, 0x30),
152 DEFINE_RES_IRQ(evt2irq(0x580)),
153 DEFINE_RES_IRQ(evt2irq(0x5a0)),
154 DEFINE_RES_IRQ(evt2irq(0x5c0)),
159 .id = 0,
172 DEFINE_RES_MEM(0xffdc0000, 0x2c),
173 DEFINE_RES_IRQ(evt2irq(0xe00)),
174 DEFINE_RES_IRQ(evt2irq(0xe20)),
175 DEFINE_RES_IRQ(evt2irq(0xe40)),
191 .offset = 0,
192 .dmars = 0,
193 .dmars_bit = 0,
195 .offset = 0x10,
196 .dmars = 0,
199 .offset = 0x20,
201 .dmars_bit = 0,
203 .offset = 0x30,
207 .offset = 0x50,
209 .dmars_bit = 0,
211 .offset = 0x60,
219 .offset = 0,
221 .offset = 0x10,
223 .offset = 0x20,
225 .offset = 0x30,
227 .offset = 0x50,
229 .offset = 0x60,
260 [0] = {
262 .start = 0xfc808020,
263 .end = 0xfc80808f,
268 .start = 0xfc809000,
269 .end = 0xfc80900b,
274 * Real DMA error vector is 0x6e0, and channel
275 * vectors are 0x620-0x6c0
278 .start = evt2irq(0x620),
279 .end = evt2irq(0x620),
285 [0] = {
287 .start = 0xfcc08020,
288 .end = 0xfcc0808f,
294 * Real DMA error vector is 0x940, and channel
295 * vectors are 0x880-0x920
298 .start = evt2irq(0x880),
299 .end = evt2irq(0x880),
306 .id = 0,
362 UNUSED = 0,
393 INTC_VECT(WDT, 0x560),
394 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
395 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
396 INTC_VECT(HUDI, 0x600),
397 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
398 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
399 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
400 INTC_VECT(DMAC0, 0x6e0),
401 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
402 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
403 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
404 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
405 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
406 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
407 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
408 INTC_VECT(DMAC1, 0x940),
409 INTC_VECT(HSPI, 0x960),
410 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
411 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
412 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
413 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
414 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
415 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
416 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
417 INTC_VECT(SIOF, 0xc00),
418 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
419 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
420 INTC_VECT(DU, 0xd80),
421 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
422 INTC_VECT(GDTA, 0xde0),
423 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
424 INTC_VECT(TMU5, 0xe40),
425 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
426 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
427 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
428 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
429 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
430 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
439 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
442 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
446 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
450 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
452 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
453 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
460 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
462 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
464 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
465 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
467 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
468 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
469 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
471 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
473 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
474 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
475 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
484 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
485 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
489 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
490 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
494 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
499 { 0xffd00024, 0, 32, /* INTREQ */
514 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
515 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
516 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
517 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
518 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
519 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
520 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
521 INTC_VECT(IRL0_HHHL, 0x3c0),
525 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
526 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
527 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
528 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
529 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
530 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
531 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
532 INTC_VECT(IRL4_HHHL, 0xcc0),
541 #define INTC_ICR0 0xffd00000
542 #define INTC_INTMSK0 0xffd00044
543 #define INTC_INTMSK1 0xffd00048
544 #define INTC_INTMSK2 0xffd40080
545 #define INTC_INTMSKCLR1 0xffd00068
546 #define INTC_INTMSKCLR2 0xffd40084
550 /* disable IRQ3-0 + IRQ7-4 */ in plat_irq_setup()
551 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
553 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
554 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
555 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
557 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
558 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
561 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
571 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); in plat_irq_setup_pins()
575 /* select IRQ mode for IRL3-0 */ in plat_irq_setup_pins()
576 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
581 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
582 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
586 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
587 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
591 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
596 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
607 setup_bootmem_node(1, 0xe55f0000, 0xe5610000); in plat_mem_setup()