Lines Matching +full:0 +full:xf20
31 #define WCN36XX_DXE_MEM_REG 0
33 #define WCN36XX_CCU_DXE_INT_SELECT_RIVA 0x310
34 #define WCN36XX_CCU_DXE_INT_SELECT_PRONTO 0x10dc
37 #define WCN36xx_DXE_CTRL_VLD BIT(0)
81 #define WCN36xx_DXE_XTYPE_H2H (0)
138 #define WCN36XX_DXE_WQ_TX_L(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17)
139 #define WCN36XX_DXE_WQ_TX_H(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17)
140 #define WCN36XX_DXE_WQ_RX_L 0xB
141 #define WCN36XX_DXE_WQ_RX_H 0x4
144 #define WCN36xx_DXE_CH_CTRL_EN BIT(0)
241 WCN36xx_DXE_CH_CTRL_SEL_SET(0) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \
245 #define WCN36XX_DXE_MEM_CSR (WCN36XX_DXE_MEM_REG + 0x00)
246 #define WCN36XX_DXE_REG_CSR_RESET (WCN36XX_DXE_MEM_REG + 0x00)
247 #define WCN36XX_DXE_ENCH_ADDR (WCN36XX_DXE_MEM_REG + 0x04)
248 #define WCN36XX_DXE_REG_CH_EN (WCN36XX_DXE_MEM_REG + 0x08)
249 #define WCN36XX_DXE_REG_CH_DONE (WCN36XX_DXE_MEM_REG + 0x0C)
250 #define WCN36XX_DXE_REG_CH_ERR (WCN36XX_DXE_MEM_REG + 0x10)
251 #define WCN36XX_DXE_INT_MASK_REG (WCN36XX_DXE_MEM_REG + 0x18)
252 #define WCN36XX_DXE_INT_SRC_RAW_REG (WCN36XX_DXE_MEM_REG + 0x20)
253 /* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */
254 /* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */
255 #define WCN36XX_DXE_INT_CH4_MASK 0x00000010
256 #define WCN36XX_DXE_INT_CH3_MASK 0x00000008
257 /* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */
258 #define WCN36XX_DXE_INT_CH1_MASK 0x00000002
259 #define WCN36XX_DXE_INT_CH0_MASK 0x00000001
260 #define WCN36XX_DXE_0_INT_CLR (WCN36XX_DXE_MEM_REG + 0x30)
261 #define WCN36XX_DXE_0_INT_ED_CLR (WCN36XX_DXE_MEM_REG + 0x34)
262 #define WCN36XX_DXE_0_INT_DONE_CLR (WCN36XX_DXE_MEM_REG + 0x38)
263 #define WCN36XX_DXE_0_INT_ERR_CLR (WCN36XX_DXE_MEM_REG + 0x3C)
265 #define WCN36XX_CH_STAT_INT_DONE_MASK 0x00008000
266 #define WCN36XX_CH_STAT_INT_ERR_MASK 0x00004000
267 #define WCN36XX_CH_STAT_INT_ED_MASK 0x00002000
269 #define WCN36XX_DXE_0_CH0_STATUS (WCN36XX_DXE_MEM_REG + 0x404)
270 #define WCN36XX_DXE_0_CH1_STATUS (WCN36XX_DXE_MEM_REG + 0x444)
271 #define WCN36XX_DXE_0_CH2_STATUS (WCN36XX_DXE_MEM_REG + 0x484)
272 #define WCN36XX_DXE_0_CH3_STATUS (WCN36XX_DXE_MEM_REG + 0x4C4)
273 #define WCN36XX_DXE_0_CH4_STATUS (WCN36XX_DXE_MEM_REG + 0x504)
275 #define WCN36XX_DXE_REG_RESET 0x5c89
278 #define WCN36XX_DXE_BMU_WQ_RX_LOW 0xB
279 #define WCN36XX_DXE_BMU_WQ_RX_HIGH 0x4
281 #define WCN36XX_DXE_TX_LOW_OFFSET 0x400
282 #define WCN36XX_DXE_TX_HIGH_OFFSET 0x500
283 #define WCN36XX_DXE_RX_LOW_OFFSET 0x440
284 #define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0
287 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C
302 #define WCN36XX_DXE_CH_SRC_ADDR 0x000C
311 #define WCN36XX_DXE_CH_DEST_ADDR 0x0014
326 #define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004
351 #define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400
352 #define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200
356 #define WCN36XX_INT_MASK_CHAN_TX_L 0x00000001
357 #define WCN36XX_INT_MASK_CHAN_RX_L 0x00000002
358 #define WCN36XX_INT_MASK_CHAN_RX_H 0x00000008
359 #define WCN36XX_INT_MASK_CHAN_TX_H 0x00000010
363 #define WCN36XX_PKT_SIZE 0xF20
384 * u32 valid :1; //0 = DMA stop, 1 = DMA continue with this
386 * u32 transfer_type :2; //0 = Host to Host space
388 * u32 bd_handling :1; //if transferType = Host to BMU, then 0
393 * u32 pdu_rel :1; //0 = don't release BD and PDUs when done,