Lines Matching +full:0 +full:xf20
20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
60 DEFINE_RES_IRQ(evt2irq(0x7e0)),
61 DEFINE_RES_IRQ(evt2irq(0x7c0)),
80 DEFINE_RES_MEM(0xffc60000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0x880)),
82 DEFINE_RES_IRQ(evt2irq(0x8a0)),
83 DEFINE_RES_IRQ(evt2irq(0x8e0)),
84 DEFINE_RES_IRQ(evt2irq(0x8c0)),
102 DEFINE_RES_MEM(0xffc10000, 0x30),
103 DEFINE_RES_IRQ(evt2irq(0x400)),
104 DEFINE_RES_IRQ(evt2irq(0x420)),
105 DEFINE_RES_IRQ(evt2irq(0x440)),
110 .id = 0,
123 DEFINE_RES_MEM(0xffc20000, 0x2c),
124 DEFINE_RES_IRQ(evt2irq(0x460)),
125 DEFINE_RES_IRQ(evt2irq(0x480)),
126 DEFINE_RES_IRQ(evt2irq(0x4a0)),
161 UNUSED = 0,
196 INTC_VECT(HUDII, 0x3e0),
197 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
198 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
199 INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
200 INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
201 INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
202 INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
203 INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
204 INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
205 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
206 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
207 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
208 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
209 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
210 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
211 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
212 INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
213 INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
214 INTC_VECT(DMAC0_DMAE, 0x9c0),
215 INTC_VECT(DU, 0x9e0),
216 INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
217 INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
218 INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
219 INTC_VECT(DMAC1_DMAE, 0xac0),
220 INTC_VECT(IIC, 0xae0),
221 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
222 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
223 INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
224 INTC_VECT(DTU0, 0xc40),
225 INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
226 INTC_VECT(DTU1, 0xca0),
227 INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
228 INTC_VECT(DTU2, 0xd00),
229 INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
230 INTC_VECT(DTU3, 0xd60),
231 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
232 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
233 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
234 INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
235 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
236 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
237 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
238 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
256 #define INT2DISTCR0 0xfe4108a0
257 #define INT2DISTCR1 0xfe4108a4
258 #define INT2DISTCR2 0xfe4108a8
261 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
263 { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
265 { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
266 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
267 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
268 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
269 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
271 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
272 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
279 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
280 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
289 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
291 { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
293 { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
296 { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
300 { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
302 { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
304 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
314 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
315 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
319 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
327 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
328 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
329 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
330 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
331 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
332 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
333 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
334 INTC_VECT(IRL_HHHL, 0x3c0),
342 int ret = 0; in plat_irq_setup_pins()
385 /* Register CPU#0 URAM space as Node 1 */ in plat_mem_setup()
386 setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */ in plat_mem_setup()
388 #if 0 in plat_mem_setup()
390 setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */ in plat_mem_setup()
391 setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */ in plat_mem_setup()
392 setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */ in plat_mem_setup()
395 setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */ in plat_mem_setup()