Lines Matching +full:0 +full:xf20
26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
90 .start = evt2irq(0x480),
103 [0] = {
104 .start = 0xffec8000,
105 .end = 0xffec80ff,
109 .start = evt2irq(0xc60),
110 .end = evt2irq(0xc60),
115 static u64 usb_ohci_dma_mask = 0xffffffffUL;
124 .coherent_dma_mask = 0xffffffff,
132 [0] = {
133 .start = 0xffec0000,
134 .end = 0xffec00ff,
138 .start = evt2irq(0xc80),
139 .end = evt2irq(0xc80),
149 .coherent_dma_mask = 0xffffffff,
160 DEFINE_RES_MEM(0xffd80000, 0x30),
161 DEFINE_RES_IRQ(evt2irq(0x580)),
162 DEFINE_RES_IRQ(evt2irq(0x5a0)),
163 DEFINE_RES_IRQ(evt2irq(0x5c0)),
168 .id = 0,
181 DEFINE_RES_MEM(0xffd88000, 0x2c),
182 DEFINE_RES_IRQ(evt2irq(0xe00)),
183 DEFINE_RES_IRQ(evt2irq(0xe20)),
184 DEFINE_RES_IRQ(evt2irq(0xe40)),
230 UNUSED = 0,
254 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
255 INTC_VECT(RTC, 0x4c0),
256 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
257 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
258 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
259 INTC_VECT(LCDC, 0x620),
260 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
261 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
262 INTC_VECT(DMAC, 0x6c0),
263 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
264 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
265 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
266 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
267 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
268 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
269 INTC_VECT(HAC, 0x980),
270 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
271 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
272 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
273 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
274 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
275 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
276 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
277 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
278 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
279 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
280 INTC_VECT(USBF, 0xca0),
281 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
282 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
283 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
284 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
285 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
286 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
287 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
288 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
289 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
290 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
291 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
292 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
293 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
302 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
303 { 0, 0, 0, 0, 0, 0, GPIO, 0,
304 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
305 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
306 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
307 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
308 { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
309 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
310 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
311 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
315 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
317 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
318 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
319 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
320 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
322 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
324 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
325 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
326 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
327 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
328 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
329 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
330 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
331 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
339 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
340 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
341 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
342 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
346 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
351 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
356 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
361 { 0xffd00024, 0, 32, /* INTREQ */
372 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
373 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
374 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
375 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
376 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
377 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
378 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
379 INTC_VECT(IRL_HHHL, 0x3c0),
383 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
391 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
392 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
405 #define INTC_ICR0 0xffd00000
406 #define INTC_INTMSK0 0xffd00044
407 #define INTC_INTMSK1 0xffd00048
408 #define INTC_INTMSK2 0xffd40080
409 #define INTC_INTMSKCLR1 0xffd00068
410 #define INTC_INTMSKCLR2 0xffd40084
414 /* disable IRQ7-0 */ in plat_irq_setup()
415 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
417 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
418 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
419 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
428 /* select IRQ mode for IRL3-0 + IRL7-4 */ in plat_irq_setup_pins()
429 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
434 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
435 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
439 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
440 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
444 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
449 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()