xref: /linux/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
161890ccaSMoudy Ho /* SPDX-License-Identifier: GPL-2.0-only */
261890ccaSMoudy Ho /*
361890ccaSMoudy Ho  * Copyright (c) 2022 MediaTek Inc.
461890ccaSMoudy Ho  * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
561890ccaSMoudy Ho  */
661890ccaSMoudy Ho 
761890ccaSMoudy Ho #ifndef __MDP_REG_RDMA_H__
861890ccaSMoudy Ho #define __MDP_REG_RDMA_H__
961890ccaSMoudy Ho 
1061890ccaSMoudy Ho #define MDP_RDMA_EN                     0x000
1161890ccaSMoudy Ho #define MDP_RDMA_RESET                  0x008
1261890ccaSMoudy Ho #define MDP_RDMA_CON                    0x020
1361890ccaSMoudy Ho #define MDP_RDMA_GMCIF_CON              0x028
1461890ccaSMoudy Ho #define MDP_RDMA_SRC_CON                0x030
1561890ccaSMoudy Ho #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE   0x060
1661890ccaSMoudy Ho #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL    0x068
1761890ccaSMoudy Ho #define MDP_RDMA_MF_SRC_SIZE            0x070
1861890ccaSMoudy Ho #define MDP_RDMA_MF_CLIP_SIZE           0x078
1961890ccaSMoudy Ho #define MDP_RDMA_MF_OFFSET_1            0x080
2061890ccaSMoudy Ho #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE   0x090
2161890ccaSMoudy Ho #define MDP_RDMA_SRC_END_0              0x100
2261890ccaSMoudy Ho #define MDP_RDMA_SRC_END_1              0x108
2361890ccaSMoudy Ho #define MDP_RDMA_SRC_END_2              0x110
2461890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_0           0x118
2561890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_1           0x120
2661890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_2           0x128
2761890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_0_P         0x148
2861890ccaSMoudy Ho #define MDP_RDMA_TRANSFORM_0            0x200
29*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_0           0x240
30*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_0    0x248
31*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_0     0x250
32*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_1           0x258
33*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_1    0x260
34*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_1     0x268
35*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_2           0x270
36*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_2    0x278
37*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_2     0x280
38*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_3           0x288
39*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_3    0x290
40*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_3     0x298
4161890ccaSMoudy Ho #define MDP_RDMA_RESV_DUMMY_0           0x2a0
4261890ccaSMoudy Ho #define MDP_RDMA_MON_STA_1              0x408
4361890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_0             0xf00
4461890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_1             0xf08
4561890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_2             0xf10
4661890ccaSMoudy Ho #define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y  0xf20
4761890ccaSMoudy Ho #define MDP_RDMA_UFO_DEC_LENGTH_BASE_C  0xf28
4861890ccaSMoudy Ho 
4961890ccaSMoudy Ho /* MASK */
5061890ccaSMoudy Ho #define MDP_RDMA_EN_MASK                    0x00000001
5161890ccaSMoudy Ho #define MDP_RDMA_RESET_MASK                 0x00000001
5261890ccaSMoudy Ho #define MDP_RDMA_CON_MASK                   0x00001110
5361890ccaSMoudy Ho #define MDP_RDMA_GMCIF_CON_MASK             0xfffb3771
5461890ccaSMoudy Ho #define MDP_RDMA_SRC_CON_MASK               0xf3ffffff
5561890ccaSMoudy Ho #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK  0x001fffff
5661890ccaSMoudy Ho #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK   0x001fffff
5761890ccaSMoudy Ho #define MDP_RDMA_MF_SRC_SIZE_MASK           0x1fff1fff
5861890ccaSMoudy Ho #define MDP_RDMA_MF_CLIP_SIZE_MASK          0x1fff1fff
5961890ccaSMoudy Ho #define MDP_RDMA_MF_OFFSET_1_MASK           0x003f001f
6061890ccaSMoudy Ho #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK  0x001fffff
6161890ccaSMoudy Ho #define MDP_RDMA_SRC_END_0_MASK             0xffffffff
6261890ccaSMoudy Ho #define MDP_RDMA_SRC_END_1_MASK             0xffffffff
6361890ccaSMoudy Ho #define MDP_RDMA_SRC_END_2_MASK             0xffffffff
6461890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_0_MASK          0xffffffff
6561890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_1_MASK          0xffffffff
6661890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_2_MASK          0xffffffff
6761890ccaSMoudy Ho #define MDP_RDMA_SRC_OFFSET_0_P_MASK        0xffffffff
6861890ccaSMoudy Ho #define MDP_RDMA_TRANSFORM_0_MASK           0xff110777
69*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_0_MASK          0x0fff00ff
70*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK   0x3fffffff
71*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK    0x3fffffff
72*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_1_MASK          0x0f7f007f
73*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK   0x3fffffff
74*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK    0x3fffffff
75*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_2_MASK          0x0f3f003f
76*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK   0x3fffffff
77*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK    0x3fffffff
78*73e00953SMoudy Ho #define MDP_RDMA_DMABUF_CON_3_MASK          0x0f3f003f
79*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK   0x3fffffff
80*73e00953SMoudy Ho #define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK    0x3fffffff
8161890ccaSMoudy Ho #define MDP_RDMA_RESV_DUMMY_0_MASK          0xffffffff
8261890ccaSMoudy Ho #define MDP_RDMA_MON_STA_1_MASK             0xffffffff
8361890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_0_MASK            0xffffffff
8461890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_1_MASK            0xffffffff
8561890ccaSMoudy Ho #define MDP_RDMA_SRC_BASE_2_MASK            0xffffffff
8661890ccaSMoudy Ho #define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y_MASK 0xffffffff
8761890ccaSMoudy Ho #define MDP_RDMA_UFO_DEC_LENGTH_BASE_C_MASK 0xffffffff
8861890ccaSMoudy Ho 
8961890ccaSMoudy Ho #endif  // __MDP_REG_RDMA_H__
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