Lines Matching +full:0 +full:xf20

6 #define INTERRUPT_CRITICAL_INPUT  0x100
9 #define INTERRUPT_DEBUG           0xd00
11 #define INTERRUPT_PERFMON         0x260
12 #define INTERRUPT_DOORBELL        0x280
16 #define INTERRUPT_MACHINE_CHECK   0x200
19 #define INTERRUPT_SYSTEM_RESET    0x100
22 #define INTERRUPT_DATA_SEGMENT    0x380
23 #define INTERRUPT_INST_SEGMENT    0x480
24 #define INTERRUPT_TRACE           0xd00
25 #define INTERRUPT_H_DATA_STORAGE  0xe00
26 #define INTERRUPT_HMI			0xe60
27 #define INTERRUPT_H_FAC_UNAVAIL   0xf80
29 #define INTERRUPT_DOORBELL        0xa00
30 #define INTERRUPT_PERFMON         0xf00
31 #define INTERRUPT_ALTIVEC_UNAVAIL	0xf20
35 #define INTERRUPT_DATA_STORAGE    0x300
36 #define INTERRUPT_INST_STORAGE    0x400
37 #define INTERRUPT_EXTERNAL		0x500
38 #define INTERRUPT_ALIGNMENT       0x600
39 #define INTERRUPT_PROGRAM         0x700
40 #define INTERRUPT_SYSCALL         0xc00
41 #define INTERRUPT_TRACE			0xd00
44 #define INTERRUPT_FP_UNAVAIL      0x800
47 #define INTERRUPT_DECREMENTER     0x900
50 #define INTERRUPT_PERFMON         0x0
54 #define INTERRUPT_SOFT_EMU_8xx		0x1000
55 #define INTERRUPT_INST_TLB_MISS_8xx	0x1100
56 #define INTERRUPT_DATA_TLB_MISS_8xx	0x1200
57 #define INTERRUPT_INST_TLB_ERROR_8xx	0x1300
58 #define INTERRUPT_DATA_TLB_ERROR_8xx	0x1400
59 #define INTERRUPT_DATA_BREAKPOINT_8xx	0x1c00
60 #define INTERRUPT_INST_BREAKPOINT_8xx	0x1d00
63 #define INTERRUPT_INST_TLB_MISS_603		0x1000
64 #define INTERRUPT_DATA_LOAD_TLB_MISS_603	0x1100
65 #define INTERRUPT_DATA_STORE_TLB_MISS_603	0x1200
86 } while (0)
111 	local_paca->srr_valid = 0;  in srr_regs_clobbered()
112 	local_paca->hsrr_valid = 0;  in srr_regs_clobbered()
117 	return 0;  in search_kernel_restart_table()
299 		 * reconcied (e.g., interrupt entry with MSR[EE]=0 but softe  in interrupt_nmi_enter_prepare()
313 		this_cpu_set_ftrace_enabled(0);  in interrupt_nmi_enter_prepare()