Lines Matching +full:0 +full:xf20
22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
103 DEFINE_RES_IRQ(evt2irq(0xa20)),
122 DEFINE_RES_MEM(0xff928000, 0x100),
123 DEFINE_RES_IRQ(evt2irq(0xa40)),
142 DEFINE_RES_MEM(0xff929000, 0x100),
143 DEFINE_RES_IRQ(evt2irq(0xa60)),
162 DEFINE_RES_MEM(0xff92a000, 0x100),
163 DEFINE_RES_IRQ(evt2irq(0xa80)),
182 DEFINE_RES_MEM(0xff92b000, 0x100),
183 DEFINE_RES_IRQ(evt2irq(0xaa0)),
202 DEFINE_RES_MEM(0xff92c000, 0x100),
203 DEFINE_RES_IRQ(evt2irq(0xac0)),
221 DEFINE_RES_MEM(0xffd80000, 0x30),
222 DEFINE_RES_IRQ(evt2irq(0x400)),
223 DEFINE_RES_IRQ(evt2irq(0x420)),
224 DEFINE_RES_IRQ(evt2irq(0x440)),
229 .id = 0,
242 DEFINE_RES_MEM(0xffd81000, 0x30),
243 DEFINE_RES_IRQ(evt2irq(0x460)),
244 DEFINE_RES_IRQ(evt2irq(0x480)),
245 DEFINE_RES_IRQ(evt2irq(0x4a0)),
263 DEFINE_RES_MEM(0xffd82000, 0x2c),
264 DEFINE_RES_IRQ(evt2irq(0x4c0)),
265 DEFINE_RES_IRQ(evt2irq(0x4e0)),
266 DEFINE_RES_IRQ(evt2irq(0x500)),
325 UNUSED = 0,
358 INTC_VECT(GPIO, 0x3e0),
359 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
360 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
361 INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
362 INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
363 INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
364 INTC_VECT(TMU8, 0x540),
365 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
366 INTC_VECT(SPDIF, 0x5e0),
367 INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
368 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
369 INTC_VECT(DMAC0_DMINT2, 0x680),
370 INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
371 INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
372 INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
373 INTC_VECT(SRC_SPDIF, 0x760),
374 INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
375 INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
376 INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
377 INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
378 INTC_VECT(GFX2D, 0x8c0),
379 INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
380 INTC_VECT(EXBUS_ATA, 0x940),
381 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
382 INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
383 INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
384 INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
385 INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
386 INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
387 INTC_VECT(ADC, 0xb20),
388 INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
389 INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
390 INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
391 INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
392 INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
393 INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
394 INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
395 INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
396 INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
397 INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
398 INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
399 INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
400 INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
401 INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
402 INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
403 INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
422 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
423 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
429 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
430 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
431 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
432 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
433 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
434 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
435 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
436 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
437 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
439 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
441 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
443 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
445 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
447 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
456 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
457 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
458 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
462 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
467 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
472 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
482 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
483 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
484 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
485 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
486 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
487 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
488 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
489 INTC_VECT(IRL_HHHL, 0x3c0),
493 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
501 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
502 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
515 #define INTC_ICR0 0xffd00000
516 #define INTC_INTMSK0 0xffd00044
517 #define INTC_INTMSK1 0xffd00048
518 #define INTC_INTMSK2 0xffd40080
519 #define INTC_INTMSKCLR1 0xffd00068
520 #define INTC_INTMSKCLR2 0xffd40084
524 /* disable IRQ7-0 */ in plat_irq_setup()
525 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
527 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
528 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
529 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
531 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
532 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
535 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
544 /* select IRQ mode for IRL3-0 + IRL7-4 */ in plat_irq_setup_pins()
545 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
550 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
551 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
555 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
556 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
560 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
565 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()