Lines Matching +full:0 +full:xf20
24 DEFINE_RES_MEM(0xffe00000, 0x100),
25 DEFINE_RES_IRQ(evt2irq(0xc00)),
30 .id = 0,
44 DEFINE_RES_MEM(0xffe10000, 0x100),
45 DEFINE_RES_IRQ(evt2irq(0xc20)),
64 DEFINE_RES_MEM(0xffe20000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0xc40)),
84 DEFINE_RES_MEM(0xffe30000, 0x100),
85 DEFINE_RES_IRQ(evt2irq(0xc60)),
99 [0] = {
101 .start = 0x04470000,
102 .end = 0x04470017,
106 .start = evt2irq(0xe00),
107 .end = evt2irq(0xe60),
114 .id = 0, /* "i2c0" clock */
120 [0] = {
122 .start = 0x04750000,
123 .end = 0x04750017,
127 .start = evt2irq(0x780),
128 .end = evt2irq(0x7e0),
142 .version = "0",
143 .irq = evt2irq(0x980),
147 [0] = {
149 .start = 0xfe900000,
150 .end = 0xfe9022eb,
160 .id = 0,
170 .version = "0",
171 .irq = evt2irq(0x8c0),
175 [0] = {
177 .start = 0xfe920000,
178 .end = 0xfe9200b7,
198 .version = "0",
199 .irq = evt2irq(0x560),
203 [0] = {
205 .start = 0xfea00000,
206 .end = 0xfea102d3,
225 .channels_mask = 0x20,
229 DEFINE_RES_MEM(0x044a0000, 0x70),
230 DEFINE_RES_IRQ(evt2irq(0xf00)),
235 .id = 0,
248 DEFINE_RES_MEM(0xffd80000, 0x2c),
249 DEFINE_RES_IRQ(evt2irq(0x400)),
250 DEFINE_RES_IRQ(evt2irq(0x420)),
251 DEFINE_RES_IRQ(evt2irq(0x440)),
256 .id = 0,
305 UNUSED = 0,
333 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
334 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
335 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
336 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
337 INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
338 INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
339 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
340 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
341 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
342 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
343 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
344 INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
345 INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
346 INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
347 INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
348 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
349 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
350 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
351 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
352 INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
353 INTC_VECT(SIO, 0xd00),
354 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
355 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
356 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
357 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
358 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
359 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
360 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
361 INTC_VECT(SIU, 0xf80),
362 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
363 INTC_VECT(TMU2, 0x440),
364 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
381 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
383 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
384 { 0, 0, 0, VPU, 0, 0, 0, MFI } },
385 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
386 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
387 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
388 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
389 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
391 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
392 { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
393 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
396 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
397 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
398 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
399 { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
400 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
402 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
403 { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
404 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
409 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
410 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
411 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
412 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
413 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
414 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
415 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
416 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
417 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
418 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
419 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
424 { 0xa414001c, 16, 2, /* ICR1 */
429 { 0xa4140024, 0, 8, /* INTREQ00 */