Lines Matching +full:0 +full:xf20
25 DEFINE_RES_MEM(0xffe00000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
31 .id = 0,
46 DEFINE_RES_MEM(0xffe10000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0xb80)),
65 DEFINE_RES_MEM(0xffd80000, 0x30),
66 DEFINE_RES_IRQ(evt2irq(0x580)),
67 DEFINE_RES_IRQ(evt2irq(0x5a0)),
68 DEFINE_RES_IRQ(evt2irq(0x5c0)),
73 .id = 0,
86 DEFINE_RES_MEM(0xffdc0000, 0x2c),
87 DEFINE_RES_IRQ(evt2irq(0xe00)),
88 DEFINE_RES_IRQ(evt2irq(0xe20)),
89 DEFINE_RES_IRQ(evt2irq(0xe40)),
103 [0] = {
104 .start = 0xffe80000,
105 .end = 0xffe80000 + 0x58 - 1,
110 .start = evt2irq(0x480),
125 .offset = 0,
126 .dmars = 0,
127 .dmars_bit = 0,
129 .offset = 0x10,
130 .dmars = 0,
133 .offset = 0x20,
135 .dmars_bit = 0,
137 .offset = 0x30,
141 .offset = 0x50,
143 .dmars_bit = 0,
145 .offset = 0x60,
153 .offset = 0,
155 .offset = 0x10,
157 .offset = 0x20,
159 .offset = 0x30,
161 .offset = 0x50,
163 .offset = 0x60,
194 [0] = {
196 .start = 0xfc808020,
197 .end = 0xfc80808f,
202 .start = 0xfc809000,
203 .end = 0xfc80900b,
208 * Real DMA error vector is 0x6c0, and channel
209 * vectors are 0x640-0x6a0, 0x780-0x7a0
212 .start = evt2irq(0x640),
213 .end = evt2irq(0x640),
219 [0] = {
221 .start = 0xfc818020,
222 .end = 0xfc81808f,
228 * Real DMA error vector is 0x6c0, and channel
229 * vectors are 0x7c0-0x7e0, 0xd80-0xde0
232 .start = evt2irq(0x7c0),
233 .end = evt2irq(0x7c0),
240 .id = 0,
294 UNUSED = 0,
315 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
316 INTC_VECT(RTC, 0x4c0),
317 INTC_VECT(WDT, 0x560),
318 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
319 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
320 INTC_VECT(HUDI, 0x600),
321 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
322 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
323 INTC_VECT(DMAC0, 0x6c0),
324 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
325 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
326 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
327 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
328 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
329 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
330 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
331 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
332 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
333 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
334 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
335 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
336 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
337 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
338 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
339 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
340 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
341 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
342 INTC_VECT(TMU5, 0xe40),
343 INTC_VECT(SSI, 0xe80),
344 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
345 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
346 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
347 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
356 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
357 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
359 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
360 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
364 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
366 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
367 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
368 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
369 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
371 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
373 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
374 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
383 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
384 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
385 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
386 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
390 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
395 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
400 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
405 { 0xffd00024, 0, 32, /* INTREQ */
416 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
417 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
418 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
419 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
420 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
421 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
422 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
423 INTC_VECT(IRL_HHHL, 0x3c0),
427 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
435 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
436 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
449 #define INTC_ICR0 0xffd00000
450 #define INTC_INTMSK0 0xffd00044
451 #define INTC_INTMSK1 0xffd00048
452 #define INTC_INTMSK2 0xffd40080
453 #define INTC_INTMSKCLR1 0xffd00068
454 #define INTC_INTMSKCLR2 0xffd40084
458 /* disable IRQ7-0 */ in plat_irq_setup()
459 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
461 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
462 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
463 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
465 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
466 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
469 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
478 /* select IRQ mode for IRL3-0 + IRL7-4 */ in plat_irq_setup_pins()
479 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
484 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
485 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
489 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
490 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
494 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
499 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()