16945 uts should use KPRINTFLIKE
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Patrick Moon

16945 uts should use KPRINTFLIKE
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Patrick Mooney <pmooney@pfmooney.com>

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16854 CPUID_PASS_IDENT is sufficient for cpuid_getsig
16907 Apply microcode updates before CPUID_PASS_BASIC
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>

16854 CPUID_PASS_IDENT is sufficient for cpuid_getsig
16907 Apply microcode updates before CPUID_PASS_BASIC
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Robert Mustacchi <rm@fingolfin.org>

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16738 viona should allow configurable packet padding
16801 viona should handle ipv6eh for csum offload
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by:

16738 viona should allow configurable packet padding
16801 viona should handle ipv6eh for csum offload
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Joshua M. Clulow <josh@sysmgr.org>

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16828 Support AMD DFv4+ UMC decoding
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: C Fraire <cfraire@me.com>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald

16828 Support AMD DFv4+ UMC decoding
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: C Fraire <cfraire@me.com>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

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16808 DF_MMIO_EXT_V4_SET_ macros incorrect
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Robert Mustacchi <rm@fingolfin.org>

16222 TSC vmware calibration could be more general
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Joshua M. Clulow <josh@sysmgr.org>
Reviewed by: Jason King <jason.brian.king@gmail.co

16222 TSC vmware calibration could be more general
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Joshua M. Clulow <josh@sysmgr.org>
Reviewed by: Jason King <jason.brian.king@gmail.com>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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16702 CCM wide mode bit moved from DF::CCMConfig4 to DF::CCDEnable in DFv4D2
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDona

16702 CCM wide mode bit moved from DF::CCMConfig4 to DF::CCDEnable in DFv4D2
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

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16701 want df register validation function
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

16686 want wider masks for AMD TOM/TOM2 MSRs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Patrick Mooney <pmooney@pfmooney.com>

16668 Add field setter macros for AMD DF::MmioPciCfg{Base,Limit}Addr{,Ext}
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Gordon Ross <

16668 Add field setter macros for AMD DF::MmioPciCfg{Base,Limit}Addr{,Ext}
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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16667 Add AMD DF::SpecialSysFunctionFabricID1/2 register definitions.
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Gordon Ross <gordon.

16667 Add AMD DF::SpecialSysFunctionFabricID1/2 register definitions.
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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16645 Core DDI function device/DMA attributes could be const
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Approved by: Patrick Mooney <pmooney@pfmoo

16645 Core DDI function device/DMA attributes could be const
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Approved by: Patrick Mooney <pmooney@pfmooney.com>

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16637 Add Zen 5 client cpuid info
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Luqman Aden <luqman@oxide.computer>
Approved by: Gordon Ross

16637 Add Zen 5 client cpuid info
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Luqman Aden <luqman@oxide.computer>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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16627 Flesh out AMD Turin chip and Zen 5 uarch revisions.
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Approved by: Dan McDonald <danmcd@mnx.io>

16573 smntemp Tctl is not degrees C
16574 smntemp CCD Tdie support
16575 ksensor/topo support for synthetic sensors
16576 want ksensor manuals
16577 libtopo sensor property translations truncate valu

16573 smntemp Tctl is not degrees C
16574 smntemp CCD Tdie support
16575 ksensor/topo support for synthetic sensors
16576 want ksensor manuals
16577 libtopo sensor property translations truncate values
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: C Fraire <cfraire@me.com>
Reviewed by: Yuri Pankov <yuri@aetern.org>
Approved by: Dan McDonald <danmcd@mnx.io>

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16587 AMD Zen DFv4D2: Fix register offset and destination FabricID bit-field widths.
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Da

16587 AMD Zen DFv4D2: Fix register offset and destination FabricID bit-field widths.
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

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16559 zen_umc maps raw DFv4 IntLvNumChan value (NPS2 4CH) to the wrong df_chan_ileave value (COD2 4CH)
16560 add constant definition for DF::MmioExtAddress shift
Reviewed by: Dan Cross <cross@oxideco

16559 zen_umc maps raw DFv4 IntLvNumChan value (NPS2 4CH) to the wrong df_chan_ileave value (COD2 4CH)
16560 add constant definition for DF::MmioExtAddress shift
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

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16461 Introduce sequence to clear Branch History Buffer (BHB)
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <Gordon.W.Ros

16461 Introduce sequence to clear Branch History Buffer (BHB)
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <Gordon.W.Ross@gmail.com>

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16407 Raphael DF revision detection is incorrect
16405 initial amdzen family 1ah and cpuid support
16406 zen topo should tolerate missing revision or ppin info
Reviewed by: Andy Fiddaman <illumos@fid

16407 Raphael DF revision detection is incorrect
16405 initial amdzen family 1ah and cpuid support
16406 zen topo should tolerate missing revision or ppin info
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Luqman Aden <luqman@oxide.computer>
Approved by: Richard Lowe <richlowe@richlowe.net>

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16413 Post-barrier Return Stack Buffer (PBRSB) fixes can be detected in HW
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by: Gordon Ross

16413 Post-barrier Return Stack Buffer (PBRSB) fixes can be detected in HW
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by: Gordon Ross <Gordon.W.Ross@gmail.com>

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16397 Re-enable VERW-using x86_md_clear() function on RFDS-afflicted Intel CPUs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Approved by: Ric

16397 Re-enable VERW-using x86_md_clear() function on RFDS-afflicted Intel CPUs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Approved by: Richard Lowe <richlowe@richlowe.net>

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15639 want more NPT bit operations in bhyve
Reviewed by: Greg Colombo <greg@oxidecomputer.com>
Reviewed by: Eliza Weisman <eliza@elizas.website>
Approved by: Dan McDonald <danmcd@mnx.io>

16244 DFv4 DRAM Offset register is incorrect
16245 Remove phoenix zen_umc support for now
Reviewed by: Keith Wesolowski <wesolows@oxide.computer>
Approved by: Dan McDonald <danmcd@mnx.io>

16139 unix: we should recognize qemu
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Reviewed by: Igor Kozhukhov <igor@dilos.org>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Rob

16139 unix: we should recognize qemu
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Reviewed by: Igor Kozhukhov <igor@dilos.org>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Robert Mustacchi <rm@fingolfin.org>

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16170 Flesh out AMD Zen4 microarchitecture (core) revisions.
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@mnx.io>