1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_SC_H 28 #define _SYS_PCI_SC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * streaming cache (sc) block soft state structure: 36 * 37 * Each pci node contains has its own private sc block structure. 38 */ 39 typedef struct sc sc_t; 40 struct sc { 41 42 pci_t *sc_pci_p; /* link back to pci soft state */ 43 44 /* 45 * control registers (psycho and schizo): 46 */ 47 volatile uint64_t *sc_ctrl_reg; 48 volatile uint64_t *sc_invl_reg; 49 volatile uint64_t *sc_sync_reg; 50 uint64_t sc_sync_reg_pa; 51 52 /* 53 * control registers (schizo only): 54 */ 55 volatile uint64_t *sc_ctx_invl_reg; 56 volatile uint64_t *sc_ctx_match_reg; 57 58 /* 59 * diagnostic access registers: 60 */ 61 volatile uint64_t *sc_data_diag_acc; 62 volatile uint64_t *sc_tag_diag_acc; 63 volatile uint64_t *sc_ltag_diag_acc; 64 65 /* 66 * Sync flag and its associated buffer. 67 */ 68 caddr_t sc_sync_flag_base; 69 volatile uint64_t *sc_sync_flag_vaddr; 70 uint64_t sc_sync_flag_pa; 71 72 kmutex_t sc_sync_mutex; /* mutex for flush/sync register */ 73 }; 74 75 #define PCI_SBUF_ENTRIES 16 /* number of i/o cache lines */ 76 #define PCI_SBUF_LINE_SIZE 64 /* size of i/o cache line */ 77 78 #define PCI_CACHE_LINE_SIZE (PCI_SBUF_LINE_SIZE / 4) 79 80 extern void sc_create(pci_t *pci_p); 81 extern void sc_destroy(pci_t *pci_p); 82 extern void sc_configure(sc_t *sc_p); 83 84 /* 85 * The most significant bit (63) of each context match register. 86 */ 87 #define SC_CMR_DIRTY_BIT 1 88 #define SC_ENTRIES 16 89 #define SC_ENT_SHIFT (64 - SC_ENTRIES) 90 91 #ifdef __cplusplus 92 } 93 #endif 94 95 #endif /* _SYS_PCI_SC_H */ 96