1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MC_H 28 #define _SYS_MC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Interface of Memory Controller driver 36 * 37 * Logical view: memory -> segment -> bank -> device group -> device 38 * physical view: mc -> device group -> device 39 * 40 * MCIOC_MEM, MCIOC_SEG, MCIOC_CTRLCONF, MCIOC_CONTROL are 41 * associated with various length struct. If given number is less than the 42 * number in kernel, kernel will update the number and return EINVAL so that 43 * user could allocate enough space for the struct and fill the right number 44 * of ids at the struct. 45 * 46 * All varaiable number ids will be paired, global and local. Global id is 47 * unique in the same object list and local id is only unique to 48 * its upper layer. For instance, one memory module group has N memory modules. 49 * local ids of this memory module group is from 0 to N - 1, but global id 50 * is unique in all memory modules. So global id will be the key in the list 51 * and pass it to driver to search. Local id will be returned to user 52 * application via ioctl. 53 */ 54 55 #define MCIOC ('M' << 8) 56 #define MCIOC_MEMCONF (MCIOC|8) 57 #define MCIOC_MEM (MCIOC|9) 58 #define MCIOC_SEG (MCIOC|10) 59 #define MCIOC_BANK (MCIOC|11) 60 #define MCIOC_DEVGRP (MCIOC|12) 61 #define MCIOC_CTRLCONF (MCIOC|13) 62 #define MCIOC_CONTROL (MCIOC|14) 63 #define MCIOC_ECFLUSH (MCIOC|15) 64 65 /* 66 * libdevinfo property name for exporting the Memory Address 67 * Decode Registers for each Logical bank. An array of [NBANK] 68 * uint64_t's is created for each memory-controller node. 69 */ 70 #define MEM_CFG_PROP_NAME "logical-bank-ma-regs" 71 72 struct mc_ids { 73 int globalid; 74 int localid; 75 }; 76 77 /* 78 * Enabled memory controller is able to get memory-layout property, and 79 * it could be with or without memory. 80 */ 81 struct mc_memconf { 82 int nmcs; /* The number of enabled memory controllers */ 83 int nsegments; /* The number of memory segments */ 84 int nbanks; /* The max. number of banks per segment */ 85 int ndevgrps; /* The max. number of device groups per mc */ 86 int ndevs; /* The max. number of devices per device group */ 87 int len_dev; /* The length of device label */ 88 int xfer_size; /* Data transfer size in CPU cache line */ 89 }; 90 91 struct mc_memory { 92 uint64_t size; /* size of physical memory */ 93 int nsegments; /* The number of memory segments */ 94 struct mc_ids segmentids[1]; /* segment ids for next iteration */ 95 }; 96 97 struct mc_segment { 98 int id; /* unique segment id */ 99 int ifactor; /* interleave factor for this segment */ 100 uint64_t base; /* starting physical address */ 101 uint64_t size; /* in bytes */ 102 int nbanks; /* The number of banks at this segment */ 103 struct mc_ids bankids[1]; /* logical bank ids for next iteration */ 104 }; 105 106 struct mc_bank { 107 int id; /* unique id for logic bank */ 108 struct mc_ids devgrpid; /* Only one device group id per logical bank */ 109 uint64_t mask; /* If (Physic Address & MASK) == MATCH, */ 110 uint64_t match; /* Physic Address is located at this bank. */ 111 uint64_t size; /* memory size per logical bank */ 112 }; 113 114 struct mc_ctrlconf { 115 int nmcs; /* The number of enabled memory controllers */ 116 struct mc_ids mcids[1]; /* mc ids for next iteration */ 117 }; 118 119 struct mc_control { 120 int id; /* unique id for memory controllers */ 121 int ndevgrps; /* The number of device groups on this mc */ 122 struct mc_ids devgrpids[1]; /* device group ids for next iteration */ 123 }; 124 125 struct mc_devgrp { 126 int id; /* unique id for device groups */ 127 int ndevices; /* The number of available devices on this dev group */ 128 uint64_t size; /* memory size per physical dimm group */ 129 }; 130 131 #ifdef __cplusplus 132 } 133 #endif 134 135 #endif /* _SYS_MC_H */ 136