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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 PCI root complex
33 -------------------
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/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
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/linux/Documentation/arch/x86/x86_64/
H A Dboot-options.rst1 .. SPDX-License-Identifier: GPL-2.0
39 Do not opt-in to Local MCE delivery. Use legacy method
55 Don't overwrite the bios-set CMCI threshold. This boot option
62 Force-enable recoverable machine check code paths
73 Use IO-APIC. Default
76 Don't use the IO-APIC.
85 See Documentation/arch/x86/i386/IO-APIC.rst
91 Don't check the IO-APIC timer. This can work around
141 pci
142 Use a write to the PCI config space register 0xcf9 to trigger reboot.
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/linux/drivers/acpi/
H A Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
8 * before their IOMMU is ready.
12 * VIOT driver looks for an IOMMU associated to the device in the VIOT table.
13 * If an IOMMU exists and has been initialized, the VIOT driver initializes the
14 * device's IOMMU fwspec, allowing the DMA infrastructure to invoke the IOMMU
15 * ops when the device driver configures DMA mappings. If an IOMMU exists and
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
17 * the device until the IOMMU is available.
23 #include <linux/iommu.h>
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/linux/arch/sparc/kernel/
H A Dpsycho_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
39 struct strbuf *strbuf = &pbm->stc; in psycho_check_stc_error()
43 if (!strbuf->strbuf_control) in psycho_check_stc_error()
46 err_base = strbuf->strbuf_err_stat; in psycho_check_stc_error()
47 tag_base = strbuf->strbuf_tag_diag; in psycho_check_stc_error()
48 line_base = strbuf->strbuf_line_diag; in psycho_check_stc_error()
55 * before re-enabling the streaming buffer. If any dirty data in psycho_check_stc_error()
60 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
61 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
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H A Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* pci_impl.h: Helper definitions for PCI controller support.
12 #include <linux/pci.h>
16 #include <asm/iommu.h>
18 /* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has its own. (ie. the IOMMU
24 * Furthermore, each PCI bus module controls its own autonomous
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
9 #include <linux/pci.h>
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
11 #include <linux/pci.h>
20 #include <asm/iommu.h>
33 /* Misc. PSYCHO PCI controller register offsets and definitions. */
49 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
51 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
55 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
57 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
61 /* Helper function of IOMMU error checking, which checks out
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H A Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_sabre.c: Sabre specific PCI controller support.
11 #include <linux/pci.h>
22 #include <asm/iommu.h>
34 /* SABRE PCI controller register offsets and definitions. */
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
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H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci.c: UltraSparc PCI controller support.
8 * OF tree based PCI bus probing taken from the PowerPC port
18 #include <linux/pci.h>
35 /* List of all PCI controllers found in the system. */
42 volatile int pci_poke_cpu = -1;
63 pci_poke_cpu = -1; in pci_config_read8()
85 pci_poke_cpu = -1; in pci_config_read16()
107 pci_poke_cpu = -1; in pci_config_read32()
128 pci_poke_cpu = -1; in pci_config_write8()
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H A Dpci_fire.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_fire.c: Sun4u platform PCI-E controller support.
7 #include <linux/pci.h>
33 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
38 /* No virtual-dma property on these guys, use largest size. */ in pci_fire_pbm_iommu_init()
45 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
46 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
48 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
53 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
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/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
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/linux/arch/x86/kernel/
H A Dpci-dma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-map-ops.h>
3 #include <linux/dma-direct.h>
4 #include <linux/iommu.h>
9 #include <linux/pci.h>
10 #include <linux/amd-iommu.h>
14 #include <asm/iommu.h>
19 #include <xen/swiotlb-xen.h>
37 /* Set this to 1 if there is a HW IOMMU in the system */
46 /* don't initialize swiotlb if iommu=off (no_iommu=1) */ in pci_swiotlb_detect()
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H A Daperture_64.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pci.h>
28 #include <asm/iommu.h>
30 #include <asm/pci-direct.h>
38 * that will do the on-position decompress, and could overlap with
46 * So don't use 512M below as gart iommu, leave the space for kernel
104 /* This code runs before the PCI subsystem is initialized, so just
121 * make the IOMMU useless. in allocate_aperture()
126 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n", in allocate_aperture()
127 addr, addr + aper_size - 1, aper_size >> 10); in allocate_aperture()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/linux/Documentation/arch/x86/
H A Diommu.rst2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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/linux/drivers/iommu/intel/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2014 Intel Corporation.
17 #include <linux/dma-direct.h>
20 #include <linux/pci.h>
21 #include <linux/pci-ats.h>
27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
38 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
39 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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/linux/drivers/iommu/amd/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # AMD IOMMU support
4 bool "AMD IOMMU support"
17 depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
19 With this option you can enable support for AMD IOMMU hardware in
20 your system. An IOMMU is a hardware component which provides
21 remapping of DMA memory accesses from devices. With an AMD IOMMU you
25 You can find out if your system has an AMD IOMMU if you look into
30 bool "Enable AMD IOMMU internals in DebugFS"
35 DO NOT ENABLE THIS OPTION UNLESS YOU REALLY, -REALLY- KNOW WHAT YOU ARE DOING!!!
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H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * AMD IOMMU driver
11 #include <linux/pci.h>
20 void amd_iommu_debugfs_setup(struct amd_iommu *iommu) in amd_iommu_debugfs_setup() argument
30 snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); in amd_iommu_debugfs_setup()
31 iommu->debugfs = debugfs_create_dir(name, amd_iommu_debugfs); in amd_iommu_debugfs_setup()
/linux/drivers/firmware/efi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 resource, and set aside for direct-access (device-dax) by
45 device-dax kmem facility. Say N to have the kernel treat this
83 memory before executing it. For compatibility with non-EFI loaders,
129 bool "Add support for Quark capsules with non-standard headers"
198 bool "Clear Busmaster bit on PCI bridges during ExitBootServices()"
200 Disable the busmaster bit in the control register on all PCI bridges
202 kernel. System firmware may configure the IOMMU to prevent malicious
203 PCI devices from being able to attack the OS via DMA. However, since
204 firmware can't guarantee that the OS is IOMMU-aware, it will tear
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