1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2a88b5ba8SSam Ravnborg /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3a88b5ba8SSam Ravnborg *
4a88b5ba8SSam Ravnborg * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
5a88b5ba8SSam Ravnborg */
6a88b5ba8SSam Ravnborg
7a88b5ba8SSam Ravnborg #include <linux/kernel.h>
8a88b5ba8SSam Ravnborg #include <linux/types.h>
9a88b5ba8SSam Ravnborg #include <linux/pci.h>
10a88b5ba8SSam Ravnborg #include <linux/init.h>
11a88b5ba8SSam Ravnborg #include <linux/slab.h>
127b64db60SPaul Gortmaker #include <linux/export.h>
13a88b5ba8SSam Ravnborg #include <linux/interrupt.h>
1461c2ef4bSRob Herring #include <linux/of.h>
1561c2ef4bSRob Herring #include <linux/of_platform.h>
1661c2ef4bSRob Herring #include <linux/platform_device.h>
1761c2ef4bSRob Herring #include <linux/property.h>
1898fa15f3SAnshuman Khandual #include <linux/numa.h>
19a88b5ba8SSam Ravnborg
20a88b5ba8SSam Ravnborg #include <asm/iommu.h>
21a88b5ba8SSam Ravnborg #include <asm/irq.h>
22a88b5ba8SSam Ravnborg #include <asm/pstate.h>
23a88b5ba8SSam Ravnborg #include <asm/prom.h>
24a88b5ba8SSam Ravnborg #include <asm/upa.h>
25a88b5ba8SSam Ravnborg
26a88b5ba8SSam Ravnborg #include "pci_impl.h"
27a88b5ba8SSam Ravnborg #include "iommu_common.h"
28a88b5ba8SSam Ravnborg
29a88b5ba8SSam Ravnborg #define DRIVER_NAME "schizo"
30a88b5ba8SSam Ravnborg #define PFX DRIVER_NAME ": "
31a88b5ba8SSam Ravnborg
32a88b5ba8SSam Ravnborg /* This is a convention that at least Excalibur and Merlin
33a88b5ba8SSam Ravnborg * follow. I suppose the SCHIZO used in Starcat and friends
34a88b5ba8SSam Ravnborg * will do similar.
35a88b5ba8SSam Ravnborg *
36a88b5ba8SSam Ravnborg * The only way I could see this changing is if the newlink
37a88b5ba8SSam Ravnborg * block requires more space in Schizo's address space than
38a88b5ba8SSam Ravnborg * they predicted, thus requiring an address space reorg when
39a88b5ba8SSam Ravnborg * the newer Schizo is taped out.
40a88b5ba8SSam Ravnborg */
41a88b5ba8SSam Ravnborg
42a88b5ba8SSam Ravnborg /* Streaming buffer control register. */
43a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
44a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
45a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
46a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
47a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
48a88b5ba8SSam Ravnborg
49a88b5ba8SSam Ravnborg /* IOMMU control register. */
50a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
51a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
52a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
53a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
54a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
55a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
56a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
61a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
62a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
63a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
64a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
65a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
66a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
67a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
68a88b5ba8SSam Ravnborg
69a88b5ba8SSam Ravnborg /* Schizo config space address format is nearly identical to
70a88b5ba8SSam Ravnborg * that of PSYCHO:
71a88b5ba8SSam Ravnborg *
72a88b5ba8SSam Ravnborg * 32 24 23 16 15 11 10 8 7 2 1 0
73a88b5ba8SSam Ravnborg * ---------------------------------------------------------
74a88b5ba8SSam Ravnborg * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
75a88b5ba8SSam Ravnborg * ---------------------------------------------------------
76a88b5ba8SSam Ravnborg */
77a88b5ba8SSam Ravnborg #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
78a88b5ba8SSam Ravnborg #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
79a88b5ba8SSam Ravnborg (((unsigned long)(BUS) << 16) | \
80a88b5ba8SSam Ravnborg ((unsigned long)(DEVFN) << 8) | \
81a88b5ba8SSam Ravnborg ((unsigned long)(REG)))
82a88b5ba8SSam Ravnborg
schizo_pci_config_mkaddr(struct pci_pbm_info * pbm,unsigned char bus,unsigned int devfn,int where)83a88b5ba8SSam Ravnborg static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
84a88b5ba8SSam Ravnborg unsigned char bus,
85a88b5ba8SSam Ravnborg unsigned int devfn,
86a88b5ba8SSam Ravnborg int where)
87a88b5ba8SSam Ravnborg {
88a88b5ba8SSam Ravnborg if (!pbm)
89a88b5ba8SSam Ravnborg return NULL;
90a88b5ba8SSam Ravnborg bus -= pbm->pci_first_busno;
91a88b5ba8SSam Ravnborg return (void *)
92a88b5ba8SSam Ravnborg (SCHIZO_CONFIG_BASE(pbm) |
93a88b5ba8SSam Ravnborg SCHIZO_CONFIG_ENCODE(bus, devfn, where));
94a88b5ba8SSam Ravnborg }
95a88b5ba8SSam Ravnborg
96a88b5ba8SSam Ravnborg /* SCHIZO error handling support. */
97a88b5ba8SSam Ravnborg enum schizo_error_type {
98a88b5ba8SSam Ravnborg UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
99a88b5ba8SSam Ravnborg };
100a88b5ba8SSam Ravnborg
101a88b5ba8SSam Ravnborg static DEFINE_SPINLOCK(stc_buf_lock);
102a88b5ba8SSam Ravnborg static unsigned long stc_error_buf[128];
103a88b5ba8SSam Ravnborg static unsigned long stc_tag_buf[16];
104a88b5ba8SSam Ravnborg static unsigned long stc_line_buf[16];
105a88b5ba8SSam Ravnborg
106a88b5ba8SSam Ravnborg #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
107a88b5ba8SSam Ravnborg #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
108a88b5ba8SSam Ravnborg #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
109a88b5ba8SSam Ravnborg #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
110a88b5ba8SSam Ravnborg #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
111a88b5ba8SSam Ravnborg
112a88b5ba8SSam Ravnborg #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
113a88b5ba8SSam Ravnborg #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
114a88b5ba8SSam Ravnborg #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
115a88b5ba8SSam Ravnborg
116a88b5ba8SSam Ravnborg #define SCHIZO_STCERR_WRITE 0x2UL
117a88b5ba8SSam Ravnborg #define SCHIZO_STCERR_READ 0x1UL
118a88b5ba8SSam Ravnborg
119a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
120a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
121a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
122a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_READ 0x4000000000000000UL
123a88b5ba8SSam Ravnborg
124a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
125a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
126a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
127a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
128a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
129a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
130a88b5ba8SSam Ravnborg
__schizo_check_stc_error_pbm(struct pci_pbm_info * pbm,enum schizo_error_type type)131a88b5ba8SSam Ravnborg static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
132a88b5ba8SSam Ravnborg enum schizo_error_type type)
133a88b5ba8SSam Ravnborg {
134a88b5ba8SSam Ravnborg struct strbuf *strbuf = &pbm->stc;
135a88b5ba8SSam Ravnborg unsigned long regbase = pbm->pbm_regs;
136a88b5ba8SSam Ravnborg unsigned long err_base, tag_base, line_base;
137a88b5ba8SSam Ravnborg u64 control;
138a88b5ba8SSam Ravnborg int i;
139a88b5ba8SSam Ravnborg
140a88b5ba8SSam Ravnborg err_base = regbase + SCHIZO_STC_ERR;
141a88b5ba8SSam Ravnborg tag_base = regbase + SCHIZO_STC_TAG;
142a88b5ba8SSam Ravnborg line_base = regbase + SCHIZO_STC_LINE;
143a88b5ba8SSam Ravnborg
144a88b5ba8SSam Ravnborg spin_lock(&stc_buf_lock);
145a88b5ba8SSam Ravnborg
146a88b5ba8SSam Ravnborg /* This is __REALLY__ dangerous. When we put the
147a88b5ba8SSam Ravnborg * streaming buffer into diagnostic mode to probe
148*3cc208ffSBjorn Helgaas * its tags and error status, we _must_ clear all
149a88b5ba8SSam Ravnborg * of the line tag valid bits before re-enabling
150a88b5ba8SSam Ravnborg * the streaming buffer. If any dirty data lives
151a88b5ba8SSam Ravnborg * in the STC when we do this, we will end up
152a88b5ba8SSam Ravnborg * invalidating it before it has a chance to reach
153a88b5ba8SSam Ravnborg * main memory.
154a88b5ba8SSam Ravnborg */
155a88b5ba8SSam Ravnborg control = upa_readq(strbuf->strbuf_control);
156a88b5ba8SSam Ravnborg upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
157a88b5ba8SSam Ravnborg strbuf->strbuf_control);
158a88b5ba8SSam Ravnborg for (i = 0; i < 128; i++) {
159a88b5ba8SSam Ravnborg unsigned long val;
160a88b5ba8SSam Ravnborg
161a88b5ba8SSam Ravnborg val = upa_readq(err_base + (i * 8UL));
162a88b5ba8SSam Ravnborg upa_writeq(0UL, err_base + (i * 8UL));
163a88b5ba8SSam Ravnborg stc_error_buf[i] = val;
164a88b5ba8SSam Ravnborg }
165a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) {
166a88b5ba8SSam Ravnborg stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
167a88b5ba8SSam Ravnborg stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
168a88b5ba8SSam Ravnborg upa_writeq(0UL, tag_base + (i * 8UL));
169a88b5ba8SSam Ravnborg upa_writeq(0UL, line_base + (i * 8UL));
170a88b5ba8SSam Ravnborg }
171a88b5ba8SSam Ravnborg
172a88b5ba8SSam Ravnborg /* OK, state is logged, exit diagnostic mode. */
173a88b5ba8SSam Ravnborg upa_writeq(control, strbuf->strbuf_control);
174a88b5ba8SSam Ravnborg
175a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) {
176a88b5ba8SSam Ravnborg int j, saw_error, first, last;
177a88b5ba8SSam Ravnborg
178a88b5ba8SSam Ravnborg saw_error = 0;
179a88b5ba8SSam Ravnborg first = i * 8;
180a88b5ba8SSam Ravnborg last = first + 8;
181a88b5ba8SSam Ravnborg for (j = first; j < last; j++) {
182a88b5ba8SSam Ravnborg unsigned long errval = stc_error_buf[j];
183a88b5ba8SSam Ravnborg if (errval != 0) {
184a88b5ba8SSam Ravnborg saw_error++;
185a88b5ba8SSam Ravnborg printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
186a88b5ba8SSam Ravnborg pbm->name,
187a88b5ba8SSam Ravnborg j,
188a88b5ba8SSam Ravnborg (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
189a88b5ba8SSam Ravnborg (errval & SCHIZO_STCERR_READ) ? 1 : 0);
190a88b5ba8SSam Ravnborg }
191a88b5ba8SSam Ravnborg }
192a88b5ba8SSam Ravnborg if (saw_error != 0) {
193a88b5ba8SSam Ravnborg unsigned long tagval = stc_tag_buf[i];
194a88b5ba8SSam Ravnborg unsigned long lineval = stc_line_buf[i];
195a88b5ba8SSam Ravnborg printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
196a88b5ba8SSam Ravnborg pbm->name,
197a88b5ba8SSam Ravnborg i,
198a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
199a88b5ba8SSam Ravnborg (tagval & SCHIZO_STCTAG_VPN),
200a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
201a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
202a88b5ba8SSam Ravnborg
203a88b5ba8SSam Ravnborg /* XXX Should spit out per-bank error information... -DaveM */
204a88b5ba8SSam Ravnborg printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
205a88b5ba8SSam Ravnborg "V(%d)FOFN(%d)]\n",
206a88b5ba8SSam Ravnborg pbm->name,
207a88b5ba8SSam Ravnborg i,
208a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
209a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
210a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
211a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
212a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
213a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
214a88b5ba8SSam Ravnborg }
215a88b5ba8SSam Ravnborg }
216a88b5ba8SSam Ravnborg
217a88b5ba8SSam Ravnborg spin_unlock(&stc_buf_lock);
218a88b5ba8SSam Ravnborg }
219a88b5ba8SSam Ravnborg
220a88b5ba8SSam Ravnborg /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
221a88b5ba8SSam Ravnborg * controller level errors.
222a88b5ba8SSam Ravnborg */
223a88b5ba8SSam Ravnborg
224a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG 0xa580UL
225a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA 0xa600UL
226a88b5ba8SSam Ravnborg
227a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
228a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
229a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
230a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
231a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
232a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
233a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
234a88b5ba8SSam Ravnborg
235a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
236a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
237a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
238a88b5ba8SSam Ravnborg
schizo_check_iommu_error_pbm(struct pci_pbm_info * pbm,enum schizo_error_type type)239a88b5ba8SSam Ravnborg static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
240a88b5ba8SSam Ravnborg enum schizo_error_type type)
241a88b5ba8SSam Ravnborg {
242a88b5ba8SSam Ravnborg struct iommu *iommu = pbm->iommu;
243a88b5ba8SSam Ravnborg unsigned long iommu_tag[16];
244a88b5ba8SSam Ravnborg unsigned long iommu_data[16];
245a88b5ba8SSam Ravnborg unsigned long flags;
246a88b5ba8SSam Ravnborg u64 control;
247a88b5ba8SSam Ravnborg int i;
248a88b5ba8SSam Ravnborg
249a88b5ba8SSam Ravnborg spin_lock_irqsave(&iommu->lock, flags);
250a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control);
251a88b5ba8SSam Ravnborg if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
252a88b5ba8SSam Ravnborg unsigned long base;
253a88b5ba8SSam Ravnborg char *type_string;
254a88b5ba8SSam Ravnborg
255a88b5ba8SSam Ravnborg /* Clear the error encountered bit. */
256a88b5ba8SSam Ravnborg control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
257a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control);
258a88b5ba8SSam Ravnborg
259a88b5ba8SSam Ravnborg switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
260a88b5ba8SSam Ravnborg case 0:
261a88b5ba8SSam Ravnborg type_string = "Protection Error";
262a88b5ba8SSam Ravnborg break;
263a88b5ba8SSam Ravnborg case 1:
264a88b5ba8SSam Ravnborg type_string = "Invalid Error";
265a88b5ba8SSam Ravnborg break;
266a88b5ba8SSam Ravnborg case 2:
267a88b5ba8SSam Ravnborg type_string = "TimeOut Error";
268a88b5ba8SSam Ravnborg break;
269a88b5ba8SSam Ravnborg case 3:
270a88b5ba8SSam Ravnborg default:
271a88b5ba8SSam Ravnborg type_string = "ECC Error";
272a88b5ba8SSam Ravnborg break;
2736cb79b3fSJoe Perches }
274a88b5ba8SSam Ravnborg printk("%s: IOMMU Error, type[%s]\n",
275a88b5ba8SSam Ravnborg pbm->name, type_string);
276a88b5ba8SSam Ravnborg
277a88b5ba8SSam Ravnborg /* Put the IOMMU into diagnostic mode and probe
278*3cc208ffSBjorn Helgaas * its TLB for entries with error status.
279a88b5ba8SSam Ravnborg *
280a88b5ba8SSam Ravnborg * It is very possible for another DVMA to occur
281a88b5ba8SSam Ravnborg * while we do this probe, and corrupt the system
282a88b5ba8SSam Ravnborg * further. But we are so screwed at this point
283a88b5ba8SSam Ravnborg * that we are likely to crash hard anyways, so
284a88b5ba8SSam Ravnborg * get as much diagnostic information to the
285a88b5ba8SSam Ravnborg * console as we can.
286a88b5ba8SSam Ravnborg */
287a88b5ba8SSam Ravnborg upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
288a88b5ba8SSam Ravnborg iommu->iommu_control);
289a88b5ba8SSam Ravnborg
290a88b5ba8SSam Ravnborg base = pbm->pbm_regs;
291a88b5ba8SSam Ravnborg
292a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) {
293a88b5ba8SSam Ravnborg iommu_tag[i] =
294a88b5ba8SSam Ravnborg upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
295a88b5ba8SSam Ravnborg iommu_data[i] =
296a88b5ba8SSam Ravnborg upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
297a88b5ba8SSam Ravnborg
298a88b5ba8SSam Ravnborg /* Now clear out the entry. */
299a88b5ba8SSam Ravnborg upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
300a88b5ba8SSam Ravnborg upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
301a88b5ba8SSam Ravnborg }
302a88b5ba8SSam Ravnborg
303a88b5ba8SSam Ravnborg /* Leave diagnostic mode. */
304a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control);
305a88b5ba8SSam Ravnborg
306a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) {
307a88b5ba8SSam Ravnborg unsigned long tag, data;
308a88b5ba8SSam Ravnborg
309a88b5ba8SSam Ravnborg tag = iommu_tag[i];
310a88b5ba8SSam Ravnborg if (!(tag & SCHIZO_IOMMU_TAG_ERR))
311a88b5ba8SSam Ravnborg continue;
312a88b5ba8SSam Ravnborg
313a88b5ba8SSam Ravnborg data = iommu_data[i];
314a88b5ba8SSam Ravnborg switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
315a88b5ba8SSam Ravnborg case 0:
316a88b5ba8SSam Ravnborg type_string = "Protection Error";
317a88b5ba8SSam Ravnborg break;
318a88b5ba8SSam Ravnborg case 1:
319a88b5ba8SSam Ravnborg type_string = "Invalid Error";
320a88b5ba8SSam Ravnborg break;
321a88b5ba8SSam Ravnborg case 2:
322a88b5ba8SSam Ravnborg type_string = "TimeOut Error";
323a88b5ba8SSam Ravnborg break;
324a88b5ba8SSam Ravnborg case 3:
325a88b5ba8SSam Ravnborg default:
326a88b5ba8SSam Ravnborg type_string = "ECC Error";
327a88b5ba8SSam Ravnborg break;
3286cb79b3fSJoe Perches }
329a88b5ba8SSam Ravnborg printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
330a88b5ba8SSam Ravnborg "sz(%dK) vpg(%08lx)]\n",
331a88b5ba8SSam Ravnborg pbm->name, i, type_string,
332a88b5ba8SSam Ravnborg (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
333a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
334a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
335a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
336a88b5ba8SSam Ravnborg (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
337a88b5ba8SSam Ravnborg printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
338a88b5ba8SSam Ravnborg pbm->name, i,
339a88b5ba8SSam Ravnborg ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
340a88b5ba8SSam Ravnborg ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
341a88b5ba8SSam Ravnborg (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
342a88b5ba8SSam Ravnborg }
343a88b5ba8SSam Ravnborg }
344a88b5ba8SSam Ravnborg if (pbm->stc.strbuf_enabled)
345a88b5ba8SSam Ravnborg __schizo_check_stc_error_pbm(pbm, type);
346a88b5ba8SSam Ravnborg spin_unlock_irqrestore(&iommu->lock, flags);
347a88b5ba8SSam Ravnborg }
348a88b5ba8SSam Ravnborg
schizo_check_iommu_error(struct pci_pbm_info * pbm,enum schizo_error_type type)349a88b5ba8SSam Ravnborg static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
350a88b5ba8SSam Ravnborg enum schizo_error_type type)
351a88b5ba8SSam Ravnborg {
352a88b5ba8SSam Ravnborg schizo_check_iommu_error_pbm(pbm, type);
353a88b5ba8SSam Ravnborg if (pbm->sibling)
354a88b5ba8SSam Ravnborg schizo_check_iommu_error_pbm(pbm->sibling, type);
355a88b5ba8SSam Ravnborg }
356a88b5ba8SSam Ravnborg
357a88b5ba8SSam Ravnborg /* Uncorrectable ECC error status gathering. */
358a88b5ba8SSam Ravnborg #define SCHIZO_UE_AFSR 0x10030UL
359a88b5ba8SSam Ravnborg #define SCHIZO_UE_AFAR 0x10038UL
360a88b5ba8SSam Ravnborg
361a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
362a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
363a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
364a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
365a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
366a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
367a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
368a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
369a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
370a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
371a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
372a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
373a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
374a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
375a88b5ba8SSam Ravnborg
schizo_ue_intr(int irq,void * dev_id)376a88b5ba8SSam Ravnborg static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
377a88b5ba8SSam Ravnborg {
378a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id;
379a88b5ba8SSam Ravnborg unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
380a88b5ba8SSam Ravnborg unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
381a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits;
382a88b5ba8SSam Ravnborg int reported, limit;
383a88b5ba8SSam Ravnborg
384a88b5ba8SSam Ravnborg /* Latch uncorrectable error status. */
385a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg);
386a88b5ba8SSam Ravnborg
387a88b5ba8SSam Ravnborg /* If either of the error pending bits are set in the
388a88b5ba8SSam Ravnborg * AFSR, the error status is being actively updated by
389a88b5ba8SSam Ravnborg * the hardware and we must re-read to get a clean value.
390a88b5ba8SSam Ravnborg */
391a88b5ba8SSam Ravnborg limit = 1000;
392a88b5ba8SSam Ravnborg do {
393a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg);
394a88b5ba8SSam Ravnborg } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
395a88b5ba8SSam Ravnborg
396a88b5ba8SSam Ravnborg /* Clear the primary/secondary error status bits. */
397a88b5ba8SSam Ravnborg error_bits = afsr &
398a88b5ba8SSam Ravnborg (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
399a88b5ba8SSam Ravnborg SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
400a88b5ba8SSam Ravnborg if (!error_bits)
401a88b5ba8SSam Ravnborg return IRQ_NONE;
402a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg);
403a88b5ba8SSam Ravnborg
404a88b5ba8SSam Ravnborg /* Log the error. */
405a88b5ba8SSam Ravnborg printk("%s: Uncorrectable Error, primary error type[%s]\n",
406a88b5ba8SSam Ravnborg pbm->name,
407a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_UEAFSR_PPIO) ?
408a88b5ba8SSam Ravnborg "PIO" :
409a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_UEAFSR_PDRD) ?
410a88b5ba8SSam Ravnborg "DMA Read" :
411a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_UEAFSR_PDWR) ?
412a88b5ba8SSam Ravnborg "DMA Write" : "???")))));
413a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
414a88b5ba8SSam Ravnborg pbm->name,
415a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
416a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
417a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
418a88b5ba8SSam Ravnborg printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
419a88b5ba8SSam Ravnborg pbm->name,
420a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
421a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
422a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
423a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
424a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
425a88b5ba8SSam Ravnborg printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
426a88b5ba8SSam Ravnborg printk("%s: UE Secondary errors [", pbm->name);
427a88b5ba8SSam Ravnborg reported = 0;
428a88b5ba8SSam Ravnborg if (afsr & SCHIZO_UEAFSR_SPIO) {
429a88b5ba8SSam Ravnborg reported++;
430a88b5ba8SSam Ravnborg printk("(PIO)");
431a88b5ba8SSam Ravnborg }
432a88b5ba8SSam Ravnborg if (afsr & SCHIZO_UEAFSR_SDMA) {
433a88b5ba8SSam Ravnborg reported++;
434a88b5ba8SSam Ravnborg printk("(DMA)");
435a88b5ba8SSam Ravnborg }
436a88b5ba8SSam Ravnborg if (!reported)
437a88b5ba8SSam Ravnborg printk("(none)");
438a88b5ba8SSam Ravnborg printk("]\n");
439a88b5ba8SSam Ravnborg
440a88b5ba8SSam Ravnborg /* Interrogate IOMMU for error status. */
441a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, UE_ERR);
442a88b5ba8SSam Ravnborg
443a88b5ba8SSam Ravnborg return IRQ_HANDLED;
444a88b5ba8SSam Ravnborg }
445a88b5ba8SSam Ravnborg
446a88b5ba8SSam Ravnborg #define SCHIZO_CE_AFSR 0x10040UL
447a88b5ba8SSam Ravnborg #define SCHIZO_CE_AFAR 0x10048UL
448a88b5ba8SSam Ravnborg
449a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
450a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
451a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
452a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
453a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
454a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
455a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
456a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
457a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
458a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
459a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
460a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
461a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
462a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
463a88b5ba8SSam Ravnborg
schizo_ce_intr(int irq,void * dev_id)464a88b5ba8SSam Ravnborg static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
465a88b5ba8SSam Ravnborg {
466a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id;
467a88b5ba8SSam Ravnborg unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
468a88b5ba8SSam Ravnborg unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
469a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits;
470a88b5ba8SSam Ravnborg int reported, limit;
471a88b5ba8SSam Ravnborg
472a88b5ba8SSam Ravnborg /* Latch error status. */
473a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg);
474a88b5ba8SSam Ravnborg
475a88b5ba8SSam Ravnborg /* If either of the error pending bits are set in the
476a88b5ba8SSam Ravnborg * AFSR, the error status is being actively updated by
477a88b5ba8SSam Ravnborg * the hardware and we must re-read to get a clean value.
478a88b5ba8SSam Ravnborg */
479a88b5ba8SSam Ravnborg limit = 1000;
480a88b5ba8SSam Ravnborg do {
481a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg);
482a88b5ba8SSam Ravnborg } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
483a88b5ba8SSam Ravnborg
484a88b5ba8SSam Ravnborg /* Clear primary/secondary error status bits. */
485a88b5ba8SSam Ravnborg error_bits = afsr &
486a88b5ba8SSam Ravnborg (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
487a88b5ba8SSam Ravnborg SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
488a88b5ba8SSam Ravnborg if (!error_bits)
489a88b5ba8SSam Ravnborg return IRQ_NONE;
490a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg);
491a88b5ba8SSam Ravnborg
492a88b5ba8SSam Ravnborg /* Log the error. */
493a88b5ba8SSam Ravnborg printk("%s: Correctable Error, primary error type[%s]\n",
494a88b5ba8SSam Ravnborg pbm->name,
495a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_CEAFSR_PPIO) ?
496a88b5ba8SSam Ravnborg "PIO" :
497a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_CEAFSR_PDRD) ?
498a88b5ba8SSam Ravnborg "DMA Read" :
499a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_CEAFSR_PDWR) ?
500a88b5ba8SSam Ravnborg "DMA Write" : "???")))));
501a88b5ba8SSam Ravnborg
502a88b5ba8SSam Ravnborg /* XXX Use syndrome and afar to print out module string just like
503a88b5ba8SSam Ravnborg * XXX UDB CE trap handler does... -DaveM
504a88b5ba8SSam Ravnborg */
505a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
506a88b5ba8SSam Ravnborg pbm->name,
507a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
508a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
509a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
510a88b5ba8SSam Ravnborg printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
511a88b5ba8SSam Ravnborg pbm->name,
512a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
513a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
514a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
515a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
516a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
517a88b5ba8SSam Ravnborg printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
518a88b5ba8SSam Ravnborg printk("%s: CE Secondary errors [", pbm->name);
519a88b5ba8SSam Ravnborg reported = 0;
520a88b5ba8SSam Ravnborg if (afsr & SCHIZO_CEAFSR_SPIO) {
521a88b5ba8SSam Ravnborg reported++;
522a88b5ba8SSam Ravnborg printk("(PIO)");
523a88b5ba8SSam Ravnborg }
524a88b5ba8SSam Ravnborg if (afsr & SCHIZO_CEAFSR_SDMA) {
525a88b5ba8SSam Ravnborg reported++;
526a88b5ba8SSam Ravnborg printk("(DMA)");
527a88b5ba8SSam Ravnborg }
528a88b5ba8SSam Ravnborg if (!reported)
529a88b5ba8SSam Ravnborg printk("(none)");
530a88b5ba8SSam Ravnborg printk("]\n");
531a88b5ba8SSam Ravnborg
532a88b5ba8SSam Ravnborg return IRQ_HANDLED;
533a88b5ba8SSam Ravnborg }
534a88b5ba8SSam Ravnborg
535a88b5ba8SSam Ravnborg #define SCHIZO_PCI_AFSR 0x2010UL
536a88b5ba8SSam Ravnborg #define SCHIZO_PCI_AFAR 0x2018UL
537a88b5ba8SSam Ravnborg
538a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
539a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
540a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
541a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
542a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
543a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
544a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
545a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
546a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
547a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
548a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
549a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
550a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
551a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
552a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
553a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
554a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
555a88b5ba8SSam Ravnborg
556a88b5ba8SSam Ravnborg #define SCHIZO_PCI_CTRL (0x2000UL)
557a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
558a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
559a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
560a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
561a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
562a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
563a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
564a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
565a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
566a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
567a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
568a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
569a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
570a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
571a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
572a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
573a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
574a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
575a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
576a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
577a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
578a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
579a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
580a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
581a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
582a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
583a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
584a88b5ba8SSam Ravnborg
schizo_pcierr_intr_other(struct pci_pbm_info * pbm)585a88b5ba8SSam Ravnborg static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
586a88b5ba8SSam Ravnborg {
587a88b5ba8SSam Ravnborg unsigned long csr_reg, csr, csr_error_bits;
588a88b5ba8SSam Ravnborg irqreturn_t ret = IRQ_NONE;
5897da89a2aSDavid S. Miller u32 stat;
590a88b5ba8SSam Ravnborg
591a88b5ba8SSam Ravnborg csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
592a88b5ba8SSam Ravnborg csr = upa_readq(csr_reg);
593a88b5ba8SSam Ravnborg csr_error_bits =
594a88b5ba8SSam Ravnborg csr & (SCHIZO_PCICTRL_BUS_UNUS |
595a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR |
596a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR |
597a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_DTO_ERR |
598a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_ERR |
599a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR);
600a88b5ba8SSam Ravnborg if (csr_error_bits) {
601a88b5ba8SSam Ravnborg /* Clear the errors. */
602a88b5ba8SSam Ravnborg upa_writeq(csr, csr_reg);
603a88b5ba8SSam Ravnborg
604a88b5ba8SSam Ravnborg /* Log 'em. */
605a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
606a88b5ba8SSam Ravnborg printk("%s: Bus unusable error asserted.\n",
607a88b5ba8SSam Ravnborg pbm->name);
608a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
609a88b5ba8SSam Ravnborg printk("%s: PCI TRDY# timeout error asserted.\n",
610a88b5ba8SSam Ravnborg pbm->name);
611a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
612a88b5ba8SSam Ravnborg printk("%s: PCI excessive retry error asserted.\n",
613a88b5ba8SSam Ravnborg pbm->name);
614a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
615a88b5ba8SSam Ravnborg printk("%s: PCI discard timeout error asserted.\n",
616a88b5ba8SSam Ravnborg pbm->name);
617a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
618a88b5ba8SSam Ravnborg printk("%s: PCI streaming byte hole error asserted.\n",
619a88b5ba8SSam Ravnborg pbm->name);
620a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_SERR)
621a88b5ba8SSam Ravnborg printk("%s: PCI SERR signal asserted.\n",
622a88b5ba8SSam Ravnborg pbm->name);
623a88b5ba8SSam Ravnborg ret = IRQ_HANDLED;
624a88b5ba8SSam Ravnborg }
6257da89a2aSDavid S. Miller pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat);
626a88b5ba8SSam Ravnborg if (stat & (PCI_STATUS_PARITY |
627a88b5ba8SSam Ravnborg PCI_STATUS_SIG_TARGET_ABORT |
628a88b5ba8SSam Ravnborg PCI_STATUS_REC_TARGET_ABORT |
629a88b5ba8SSam Ravnborg PCI_STATUS_REC_MASTER_ABORT |
630a88b5ba8SSam Ravnborg PCI_STATUS_SIG_SYSTEM_ERROR)) {
631a88b5ba8SSam Ravnborg printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
632a88b5ba8SSam Ravnborg pbm->name, stat);
6337da89a2aSDavid S. Miller pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff);
634a88b5ba8SSam Ravnborg ret = IRQ_HANDLED;
635a88b5ba8SSam Ravnborg }
636a88b5ba8SSam Ravnborg return ret;
637a88b5ba8SSam Ravnborg }
638a88b5ba8SSam Ravnborg
schizo_pcierr_intr(int irq,void * dev_id)639a88b5ba8SSam Ravnborg static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
640a88b5ba8SSam Ravnborg {
641a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id;
642a88b5ba8SSam Ravnborg unsigned long afsr_reg, afar_reg, base;
643a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits;
644a88b5ba8SSam Ravnborg int reported;
645a88b5ba8SSam Ravnborg
646a88b5ba8SSam Ravnborg base = pbm->pbm_regs;
647a88b5ba8SSam Ravnborg
648a88b5ba8SSam Ravnborg afsr_reg = base + SCHIZO_PCI_AFSR;
649a88b5ba8SSam Ravnborg afar_reg = base + SCHIZO_PCI_AFAR;
650a88b5ba8SSam Ravnborg
651a88b5ba8SSam Ravnborg /* Latch error status. */
652a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg);
653a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg);
654a88b5ba8SSam Ravnborg
655a88b5ba8SSam Ravnborg /* Clear primary/secondary error status bits. */
656a88b5ba8SSam Ravnborg error_bits = afsr &
657a88b5ba8SSam Ravnborg (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
658a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
659a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
660a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
661a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
662a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
663a88b5ba8SSam Ravnborg if (!error_bits)
664a88b5ba8SSam Ravnborg return schizo_pcierr_intr_other(pbm);
665a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg);
666a88b5ba8SSam Ravnborg
667a88b5ba8SSam Ravnborg /* Log the error. */
668a88b5ba8SSam Ravnborg printk("%s: PCI Error, primary error type[%s]\n",
669a88b5ba8SSam Ravnborg pbm->name,
670a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_PCIAFSR_PMA) ?
671a88b5ba8SSam Ravnborg "Master Abort" :
672a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PTA) ?
673a88b5ba8SSam Ravnborg "Target Abort" :
674a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
675a88b5ba8SSam Ravnborg "Excessive Retries" :
676a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
677a88b5ba8SSam Ravnborg "Parity Error" :
678a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
679a88b5ba8SSam Ravnborg "Timeout" :
680a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
681a88b5ba8SSam Ravnborg "Bus Unusable" : "???"))))))));
682a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
683a88b5ba8SSam Ravnborg pbm->name,
684a88b5ba8SSam Ravnborg (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
685a88b5ba8SSam Ravnborg (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
686a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_CFG) ?
687a88b5ba8SSam Ravnborg "Config" :
688a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_MEM) ?
689a88b5ba8SSam Ravnborg "Memory" :
690a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_IO) ?
691a88b5ba8SSam Ravnborg "I/O" : "???"))));
692a88b5ba8SSam Ravnborg printk("%s: PCI AFAR [%016lx]\n",
693a88b5ba8SSam Ravnborg pbm->name, afar);
694a88b5ba8SSam Ravnborg printk("%s: PCI Secondary errors [",
695a88b5ba8SSam Ravnborg pbm->name);
696a88b5ba8SSam Ravnborg reported = 0;
697a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SMA) {
698a88b5ba8SSam Ravnborg reported++;
699a88b5ba8SSam Ravnborg printk("(Master Abort)");
700a88b5ba8SSam Ravnborg }
701a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_STA) {
702a88b5ba8SSam Ravnborg reported++;
703a88b5ba8SSam Ravnborg printk("(Target Abort)");
704a88b5ba8SSam Ravnborg }
705a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SRTRY) {
706a88b5ba8SSam Ravnborg reported++;
707a88b5ba8SSam Ravnborg printk("(Excessive Retries)");
708a88b5ba8SSam Ravnborg }
709a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SPERR) {
710a88b5ba8SSam Ravnborg reported++;
711a88b5ba8SSam Ravnborg printk("(Parity Error)");
712a88b5ba8SSam Ravnborg }
713a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_STTO) {
714a88b5ba8SSam Ravnborg reported++;
715a88b5ba8SSam Ravnborg printk("(Timeout)");
716a88b5ba8SSam Ravnborg }
717a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SUNUS) {
718a88b5ba8SSam Ravnborg reported++;
719a88b5ba8SSam Ravnborg printk("(Bus Unusable)");
720a88b5ba8SSam Ravnborg }
721a88b5ba8SSam Ravnborg if (!reported)
722a88b5ba8SSam Ravnborg printk("(none)");
723a88b5ba8SSam Ravnborg printk("]\n");
724a88b5ba8SSam Ravnborg
725a88b5ba8SSam Ravnborg /* For the error types shown, scan PBM's PCI bus for devices
726a88b5ba8SSam Ravnborg * which have logged that error type.
727a88b5ba8SSam Ravnborg */
728a88b5ba8SSam Ravnborg
729a88b5ba8SSam Ravnborg /* If we see a Target Abort, this could be the result of an
730a88b5ba8SSam Ravnborg * IOMMU translation error of some sort. It is extremely
731a88b5ba8SSam Ravnborg * useful to log this information as usually it indicates
732a88b5ba8SSam Ravnborg * a bug in the IOMMU support code or a PCI device driver.
733a88b5ba8SSam Ravnborg */
734a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
735a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, PCI_ERR);
736a88b5ba8SSam Ravnborg pci_scan_for_target_abort(pbm, pbm->pci_bus);
737a88b5ba8SSam Ravnborg }
738a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
739a88b5ba8SSam Ravnborg pci_scan_for_master_abort(pbm, pbm->pci_bus);
740a88b5ba8SSam Ravnborg
741a88b5ba8SSam Ravnborg /* For excessive retries, PSYCHO/PBM will abort the device
742a88b5ba8SSam Ravnborg * and there is no way to specifically check for excessive
743a88b5ba8SSam Ravnborg * retries in the config space status registers. So what
744a88b5ba8SSam Ravnborg * we hope is that we'll catch it via the master/target
745a88b5ba8SSam Ravnborg * abort events.
746a88b5ba8SSam Ravnborg */
747a88b5ba8SSam Ravnborg
748a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
749a88b5ba8SSam Ravnborg pci_scan_for_parity_error(pbm, pbm->pci_bus);
750a88b5ba8SSam Ravnborg
751a88b5ba8SSam Ravnborg return IRQ_HANDLED;
752a88b5ba8SSam Ravnborg }
753a88b5ba8SSam Ravnborg
754a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_ERRLOG 0x10018UL
755a88b5ba8SSam Ravnborg
756a88b5ba8SSam Ravnborg #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
757a88b5ba8SSam Ravnborg
758a88b5ba8SSam Ravnborg #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
759a88b5ba8SSam Ravnborg #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
760a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
761a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
762a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
763a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
764a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
765a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
766a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
767a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
768a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
769a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
770a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
771a88b5ba8SSam Ravnborg #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
772a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
773a88b5ba8SSam Ravnborg #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
774a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
775a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
776a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
777a88b5ba8SSam Ravnborg #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
778a88b5ba8SSam Ravnborg #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
779a88b5ba8SSam Ravnborg #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
780a88b5ba8SSam Ravnborg #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
781a88b5ba8SSam Ravnborg #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
782a88b5ba8SSam Ravnborg #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
783a88b5ba8SSam Ravnborg #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
784a88b5ba8SSam Ravnborg #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
785a88b5ba8SSam Ravnborg #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
786a88b5ba8SSam Ravnborg #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
787a88b5ba8SSam Ravnborg #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
788a88b5ba8SSam Ravnborg #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
789a88b5ba8SSam Ravnborg
790a88b5ba8SSam Ravnborg /* We only expect UNMAP errors here. The rest of the Safari errors
791a88b5ba8SSam Ravnborg * are marked fatal and thus cause a system reset.
792a88b5ba8SSam Ravnborg */
schizo_safarierr_intr(int irq,void * dev_id)793a88b5ba8SSam Ravnborg static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
794a88b5ba8SSam Ravnborg {
795a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id;
796a88b5ba8SSam Ravnborg u64 errlog;
797a88b5ba8SSam Ravnborg
798a88b5ba8SSam Ravnborg errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
799a88b5ba8SSam Ravnborg upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
800a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
801a88b5ba8SSam Ravnborg
802a88b5ba8SSam Ravnborg if (!(errlog & BUS_ERROR_UNMAP)) {
80390181136SSam Ravnborg printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
804a88b5ba8SSam Ravnborg pbm->name, errlog);
805a88b5ba8SSam Ravnborg
806a88b5ba8SSam Ravnborg return IRQ_HANDLED;
807a88b5ba8SSam Ravnborg }
808a88b5ba8SSam Ravnborg
809a88b5ba8SSam Ravnborg printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
810a88b5ba8SSam Ravnborg pbm->name);
811a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, SAFARI_ERR);
812a88b5ba8SSam Ravnborg
813a88b5ba8SSam Ravnborg return IRQ_HANDLED;
814a88b5ba8SSam Ravnborg }
815a88b5ba8SSam Ravnborg
816a88b5ba8SSam Ravnborg /* Nearly identical to PSYCHO equivalents... */
817a88b5ba8SSam Ravnborg #define SCHIZO_ECC_CTRL 0x10020UL
818a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
819a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
820a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
821a88b5ba8SSam Ravnborg
822a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
823a88b5ba8SSam Ravnborg #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
824a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
825a88b5ba8SSam Ravnborg #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
826a88b5ba8SSam Ravnborg
pbm_routes_this_ino(struct pci_pbm_info * pbm,u32 ino)827a88b5ba8SSam Ravnborg static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
828a88b5ba8SSam Ravnborg {
829a88b5ba8SSam Ravnborg ino &= IMAP_INO;
830a88b5ba8SSam Ravnborg
831a88b5ba8SSam Ravnborg if (pbm->ino_bitmap & (1UL << ino))
832a88b5ba8SSam Ravnborg return 1;
833a88b5ba8SSam Ravnborg
834a88b5ba8SSam Ravnborg return 0;
835a88b5ba8SSam Ravnborg }
836a88b5ba8SSam Ravnborg
837a88b5ba8SSam Ravnborg /* How the Tomatillo IRQs are routed around is pure guesswork here.
838a88b5ba8SSam Ravnborg *
839a88b5ba8SSam Ravnborg * All the Tomatillo devices I see in prtconf dumps seem to have only
840a88b5ba8SSam Ravnborg * a single PCI bus unit attached to it. It would seem they are separate
841a88b5ba8SSam Ravnborg * devices because their PortID (ie. JBUS ID) values are all different
842a88b5ba8SSam Ravnborg * and thus the registers are mapped to totally different locations.
843a88b5ba8SSam Ravnborg *
844a88b5ba8SSam Ravnborg * However, two Tomatillo's look "similar" in that the only difference
845a88b5ba8SSam Ravnborg * in their PortID is the lowest bit.
846a88b5ba8SSam Ravnborg *
847a88b5ba8SSam Ravnborg * So if we were to ignore this lower bit, it certainly looks like two
848a88b5ba8SSam Ravnborg * PCI bus units of the same Tomatillo. I still have not really
849a88b5ba8SSam Ravnborg * figured this out...
850a88b5ba8SSam Ravnborg */
tomatillo_register_error_handlers(struct pci_pbm_info * pbm)851a88b5ba8SSam Ravnborg static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
852a88b5ba8SSam Ravnborg {
853cd4cd730SGrant Likely struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
854a88b5ba8SSam Ravnborg u64 tmp, err_mask, err_no_mask;
855a88b5ba8SSam Ravnborg int err;
856a88b5ba8SSam Ravnborg
857a88b5ba8SSam Ravnborg /* Tomatillo IRQ property layout is:
858a88b5ba8SSam Ravnborg * 0: PCIERR
859a88b5ba8SSam Ravnborg * 1: UE ERR
860a88b5ba8SSam Ravnborg * 2: CE ERR
861a88b5ba8SSam Ravnborg * 3: SERR
862a88b5ba8SSam Ravnborg * 4: POWER FAIL?
863a88b5ba8SSam Ravnborg */
864a88b5ba8SSam Ravnborg
865a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
8661636f8acSGrant Likely err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
867a88b5ba8SSam Ravnborg "TOMATILLO_UE", pbm);
868a88b5ba8SSam Ravnborg if (err)
869a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register UE, "
870a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
871a88b5ba8SSam Ravnborg }
872a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
8731636f8acSGrant Likely err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
874a88b5ba8SSam Ravnborg "TOMATILLO_CE", pbm);
875a88b5ba8SSam Ravnborg if (err)
876a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register CE, "
877a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
878a88b5ba8SSam Ravnborg }
879a88b5ba8SSam Ravnborg err = 0;
880a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
8811636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
882a88b5ba8SSam Ravnborg "TOMATILLO_PCIERR", pbm);
883a88b5ba8SSam Ravnborg } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
8841636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
885a88b5ba8SSam Ravnborg "TOMATILLO_PCIERR", pbm);
886a88b5ba8SSam Ravnborg }
887a88b5ba8SSam Ravnborg if (err)
888a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register PCIERR, "
889a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
890a88b5ba8SSam Ravnborg
891a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
8921636f8acSGrant Likely err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
893a88b5ba8SSam Ravnborg "TOMATILLO_SERR", pbm);
894a88b5ba8SSam Ravnborg if (err)
895a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register SERR, "
896a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
897a88b5ba8SSam Ravnborg }
898a88b5ba8SSam Ravnborg
899a88b5ba8SSam Ravnborg /* Enable UE and CE interrupts for controller. */
900a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_ECCCTRL_EE |
901a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_UE |
902a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
903a88b5ba8SSam Ravnborg
904a88b5ba8SSam Ravnborg /* Enable PCI Error interrupts and clear error
905a88b5ba8SSam Ravnborg * bits.
906a88b5ba8SSam Ravnborg */
907a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
908a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR |
909a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR |
910a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR |
911a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_EEN);
912a88b5ba8SSam Ravnborg
913a88b5ba8SSam Ravnborg err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
914a88b5ba8SSam Ravnborg
915a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
916a88b5ba8SSam Ravnborg tmp |= err_mask;
917a88b5ba8SSam Ravnborg tmp &= ~err_no_mask;
918a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
919a88b5ba8SSam Ravnborg
920a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
921a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
922a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO |
923a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
924a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
925a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO);
926a88b5ba8SSam Ravnborg
927a88b5ba8SSam Ravnborg upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
928a88b5ba8SSam Ravnborg
929a88b5ba8SSam Ravnborg err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
930a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
931a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
932a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
933a88b5ba8SSam Ravnborg BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
934a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
935a88b5ba8SSam Ravnborg BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
936a88b5ba8SSam Ravnborg BUS_ERROR_APERR | BUS_ERROR_UNMAP |
937a88b5ba8SSam Ravnborg BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
938a88b5ba8SSam Ravnborg
939a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
940a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
941a88b5ba8SSam Ravnborg
942a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
943a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
944a88b5ba8SSam Ravnborg }
945a88b5ba8SSam Ravnborg
schizo_register_error_handlers(struct pci_pbm_info * pbm)946a88b5ba8SSam Ravnborg static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
947a88b5ba8SSam Ravnborg {
948cd4cd730SGrant Likely struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
949a88b5ba8SSam Ravnborg u64 tmp, err_mask, err_no_mask;
950a88b5ba8SSam Ravnborg int err;
951a88b5ba8SSam Ravnborg
952a88b5ba8SSam Ravnborg /* Schizo IRQ property layout is:
953a88b5ba8SSam Ravnborg * 0: PCIERR
954a88b5ba8SSam Ravnborg * 1: UE ERR
955a88b5ba8SSam Ravnborg * 2: CE ERR
956a88b5ba8SSam Ravnborg * 3: SERR
957a88b5ba8SSam Ravnborg * 4: POWER FAIL?
958a88b5ba8SSam Ravnborg */
959a88b5ba8SSam Ravnborg
960a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
9611636f8acSGrant Likely err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
962a88b5ba8SSam Ravnborg "SCHIZO_UE", pbm);
963a88b5ba8SSam Ravnborg if (err)
964a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register UE, "
965a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
966a88b5ba8SSam Ravnborg }
967a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
9681636f8acSGrant Likely err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
969a88b5ba8SSam Ravnborg "SCHIZO_CE", pbm);
970a88b5ba8SSam Ravnborg if (err)
971a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register CE, "
972a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
973a88b5ba8SSam Ravnborg }
974a88b5ba8SSam Ravnborg err = 0;
975a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
9761636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
977a88b5ba8SSam Ravnborg "SCHIZO_PCIERR", pbm);
978a88b5ba8SSam Ravnborg } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
9791636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
980a88b5ba8SSam Ravnborg "SCHIZO_PCIERR", pbm);
981a88b5ba8SSam Ravnborg }
982a88b5ba8SSam Ravnborg if (err)
983a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register PCIERR, "
984a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
985a88b5ba8SSam Ravnborg
986a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
9871636f8acSGrant Likely err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
988a88b5ba8SSam Ravnborg "SCHIZO_SERR", pbm);
989a88b5ba8SSam Ravnborg if (err)
990a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register SERR, "
991a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err);
992a88b5ba8SSam Ravnborg }
993a88b5ba8SSam Ravnborg
994a88b5ba8SSam Ravnborg /* Enable UE and CE interrupts for controller. */
995a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_ECCCTRL_EE |
996a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_UE |
997a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
998a88b5ba8SSam Ravnborg
999a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1000a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_ESLCK |
1001a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR |
1002a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR |
1003a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_ERR |
1004a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR |
1005a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_EEN);
1006a88b5ba8SSam Ravnborg
1007a88b5ba8SSam Ravnborg err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1008a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_INT);
1009a88b5ba8SSam Ravnborg
1010a88b5ba8SSam Ravnborg /* Enable PCI Error interrupts and clear error
1011a88b5ba8SSam Ravnborg * bits for each PBM.
1012a88b5ba8SSam Ravnborg */
1013a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1014a88b5ba8SSam Ravnborg tmp |= err_mask;
1015a88b5ba8SSam Ravnborg tmp &= ~err_no_mask;
1016a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1017a88b5ba8SSam Ravnborg
1018a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1019a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1020a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1021a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1022a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1023a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1024a88b5ba8SSam Ravnborg pbm->pbm_regs + SCHIZO_PCI_AFSR);
1025a88b5ba8SSam Ravnborg
1026a88b5ba8SSam Ravnborg /* Make all Safari error conditions fatal except unmapped
1027a88b5ba8SSam Ravnborg * errors which we make generate interrupts.
1028a88b5ba8SSam Ravnborg */
1029a88b5ba8SSam Ravnborg err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1030a88b5ba8SSam Ravnborg BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1031a88b5ba8SSam Ravnborg BUS_ERROR_BADMC |
1032a88b5ba8SSam Ravnborg BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1033a88b5ba8SSam Ravnborg BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1034a88b5ba8SSam Ravnborg BUS_ERROR_CIQTO |
1035a88b5ba8SSam Ravnborg BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1036a88b5ba8SSam Ravnborg BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1037a88b5ba8SSam Ravnborg BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1038a88b5ba8SSam Ravnborg BUS_ERROR_ILL);
1039a88b5ba8SSam Ravnborg #if 1
1040a88b5ba8SSam Ravnborg /* XXX Something wrong with some Excalibur systems
1041a88b5ba8SSam Ravnborg * XXX Sun is shipping. The behavior on a 2-cpu
1042a88b5ba8SSam Ravnborg * XXX machine is that both CPU1 parity error bits
1043a88b5ba8SSam Ravnborg * XXX are set and are immediately set again when
1044a88b5ba8SSam Ravnborg * XXX their error status bits are cleared. Just
1045a88b5ba8SSam Ravnborg * XXX ignore them for now. -DaveM
1046a88b5ba8SSam Ravnborg */
1047a88b5ba8SSam Ravnborg err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1048a88b5ba8SSam Ravnborg BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1049a88b5ba8SSam Ravnborg #endif
1050a88b5ba8SSam Ravnborg
1051a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1052a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1053a88b5ba8SSam Ravnborg }
1054a88b5ba8SSam Ravnborg
pbm_config_busmastering(struct pci_pbm_info * pbm)1055a88b5ba8SSam Ravnborg static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1056a88b5ba8SSam Ravnborg {
1057a88b5ba8SSam Ravnborg u8 *addr;
1058a88b5ba8SSam Ravnborg
1059a88b5ba8SSam Ravnborg /* Set cache-line size to 64 bytes, this is actually
1060a88b5ba8SSam Ravnborg * a nop but I do it for completeness.
1061a88b5ba8SSam Ravnborg */
1062a88b5ba8SSam Ravnborg addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1063a88b5ba8SSam Ravnborg 0, PCI_CACHE_LINE_SIZE);
1064a88b5ba8SSam Ravnborg pci_config_write8(addr, 64 / sizeof(u32));
1065a88b5ba8SSam Ravnborg
1066a88b5ba8SSam Ravnborg /* Set PBM latency timer to 64 PCI clocks. */
1067a88b5ba8SSam Ravnborg addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1068a88b5ba8SSam Ravnborg 0, PCI_LATENCY_TIMER);
1069a88b5ba8SSam Ravnborg pci_config_write8(addr, 64);
1070a88b5ba8SSam Ravnborg }
1071a88b5ba8SSam Ravnborg
schizo_scan_bus(struct pci_pbm_info * pbm,struct device * parent)1072b7c13f76SSam Ravnborg static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
1073a88b5ba8SSam Ravnborg {
1074a88b5ba8SSam Ravnborg pbm_config_busmastering(pbm);
1075a88b5ba8SSam Ravnborg pbm->is_66mhz_capable =
107661c7a080SGrant Likely (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
1077a88b5ba8SSam Ravnborg != NULL);
1078a88b5ba8SSam Ravnborg
1079a88b5ba8SSam Ravnborg pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1080a88b5ba8SSam Ravnborg
1081a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1082a88b5ba8SSam Ravnborg tomatillo_register_error_handlers(pbm);
1083a88b5ba8SSam Ravnborg else
1084a88b5ba8SSam Ravnborg schizo_register_error_handlers(pbm);
1085a88b5ba8SSam Ravnborg }
1086a88b5ba8SSam Ravnborg
1087a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1088a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1089a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1090a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1091a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1092a88b5ba8SSam Ravnborg
schizo_pbm_strbuf_init(struct pci_pbm_info * pbm)1093a88b5ba8SSam Ravnborg static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1094a88b5ba8SSam Ravnborg {
1095a88b5ba8SSam Ravnborg unsigned long base = pbm->pbm_regs;
1096a88b5ba8SSam Ravnborg u64 control;
1097a88b5ba8SSam Ravnborg
1098a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1099a88b5ba8SSam Ravnborg /* TOMATILLO lacks streaming cache. */
1100a88b5ba8SSam Ravnborg return;
1101a88b5ba8SSam Ravnborg }
1102a88b5ba8SSam Ravnborg
1103a88b5ba8SSam Ravnborg /* SCHIZO has context flushing. */
1104a88b5ba8SSam Ravnborg pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1105a88b5ba8SSam Ravnborg pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1106a88b5ba8SSam Ravnborg pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1107a88b5ba8SSam Ravnborg pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1108a88b5ba8SSam Ravnborg pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1109a88b5ba8SSam Ravnborg
1110a88b5ba8SSam Ravnborg pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1111a88b5ba8SSam Ravnborg ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1112a88b5ba8SSam Ravnborg + 63UL)
1113a88b5ba8SSam Ravnborg & ~63UL);
1114a88b5ba8SSam Ravnborg pbm->stc.strbuf_flushflag_pa = (unsigned long)
1115a88b5ba8SSam Ravnborg __pa(pbm->stc.strbuf_flushflag);
1116a88b5ba8SSam Ravnborg
1117a88b5ba8SSam Ravnborg /* Turn off LRU locking and diag mode, enable the
1118a88b5ba8SSam Ravnborg * streaming buffer and leave the rerun-disable
1119a88b5ba8SSam Ravnborg * setting however OBP set it.
1120a88b5ba8SSam Ravnborg */
1121a88b5ba8SSam Ravnborg control = upa_readq(pbm->stc.strbuf_control);
1122a88b5ba8SSam Ravnborg control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1123a88b5ba8SSam Ravnborg SCHIZO_STRBUF_CTRL_LENAB |
1124a88b5ba8SSam Ravnborg SCHIZO_STRBUF_CTRL_DENAB);
1125a88b5ba8SSam Ravnborg control |= SCHIZO_STRBUF_CTRL_ENAB;
1126a88b5ba8SSam Ravnborg upa_writeq(control, pbm->stc.strbuf_control);
1127a88b5ba8SSam Ravnborg
1128a88b5ba8SSam Ravnborg pbm->stc.strbuf_enabled = 1;
1129a88b5ba8SSam Ravnborg }
1130a88b5ba8SSam Ravnborg
1131a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1132a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1133a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1134a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1135a88b5ba8SSam Ravnborg
schizo_pbm_iommu_init(struct pci_pbm_info * pbm)1136a88b5ba8SSam Ravnborg static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1137a88b5ba8SSam Ravnborg {
1138a88b5ba8SSam Ravnborg static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1139a88b5ba8SSam Ravnborg unsigned long i, tagbase, database;
1140a88b5ba8SSam Ravnborg struct iommu *iommu = pbm->iommu;
1141a88b5ba8SSam Ravnborg int tsbsize, err;
1142a88b5ba8SSam Ravnborg const u32 *vdma;
1143a88b5ba8SSam Ravnborg u32 dma_mask;
1144a88b5ba8SSam Ravnborg u64 control;
1145a88b5ba8SSam Ravnborg
114661c7a080SGrant Likely vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
1147a88b5ba8SSam Ravnborg if (!vdma)
1148a88b5ba8SSam Ravnborg vdma = vdma_default;
1149a88b5ba8SSam Ravnborg
1150a88b5ba8SSam Ravnborg dma_mask = vdma[0];
1151a88b5ba8SSam Ravnborg switch (vdma[1]) {
1152a88b5ba8SSam Ravnborg case 0x20000000:
1153a88b5ba8SSam Ravnborg dma_mask |= 0x1fffffff;
1154a88b5ba8SSam Ravnborg tsbsize = 64;
1155a88b5ba8SSam Ravnborg break;
1156a88b5ba8SSam Ravnborg
1157a88b5ba8SSam Ravnborg case 0x40000000:
1158a88b5ba8SSam Ravnborg dma_mask |= 0x3fffffff;
1159a88b5ba8SSam Ravnborg tsbsize = 128;
1160a88b5ba8SSam Ravnborg break;
1161a88b5ba8SSam Ravnborg
1162a88b5ba8SSam Ravnborg case 0x80000000:
1163a88b5ba8SSam Ravnborg dma_mask |= 0x7fffffff;
1164a88b5ba8SSam Ravnborg tsbsize = 128;
1165a88b5ba8SSam Ravnborg break;
1166a88b5ba8SSam Ravnborg
1167a88b5ba8SSam Ravnborg default:
1168a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1169a88b5ba8SSam Ravnborg return -EINVAL;
1170a88b5ba8SSam Ravnborg }
1171a88b5ba8SSam Ravnborg
1172a88b5ba8SSam Ravnborg /* Register addresses, SCHIZO has iommu ctx flushing. */
1173a88b5ba8SSam Ravnborg iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1174a88b5ba8SSam Ravnborg iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1175a88b5ba8SSam Ravnborg iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1176a88b5ba8SSam Ravnborg iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1177a88b5ba8SSam Ravnborg iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1178a88b5ba8SSam Ravnborg
1179a88b5ba8SSam Ravnborg /* We use the main control/status register of SCHIZO as the write
1180a88b5ba8SSam Ravnborg * completion register.
1181a88b5ba8SSam Ravnborg */
1182a88b5ba8SSam Ravnborg iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1183a88b5ba8SSam Ravnborg
1184a88b5ba8SSam Ravnborg /*
1185a88b5ba8SSam Ravnborg * Invalidate TLB Entries.
1186a88b5ba8SSam Ravnborg */
1187a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control);
1188a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_CTRL_DENAB;
1189a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control);
1190a88b5ba8SSam Ravnborg
1191a88b5ba8SSam Ravnborg tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1192a88b5ba8SSam Ravnborg
1193a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) {
1194a88b5ba8SSam Ravnborg upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1195a88b5ba8SSam Ravnborg upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1196a88b5ba8SSam Ravnborg }
1197a88b5ba8SSam Ravnborg
1198a88b5ba8SSam Ravnborg /* Leave diag mode enabled for full-flushing done
1199a88b5ba8SSam Ravnborg * in pci_iommu.c
1200a88b5ba8SSam Ravnborg */
1201a88b5ba8SSam Ravnborg err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1202a88b5ba8SSam Ravnborg pbm->numa_node);
1203a88b5ba8SSam Ravnborg if (err) {
1204a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1205a88b5ba8SSam Ravnborg return err;
1206a88b5ba8SSam Ravnborg }
1207a88b5ba8SSam Ravnborg
1208a88b5ba8SSam Ravnborg upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1209a88b5ba8SSam Ravnborg
1210a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control);
1211a88b5ba8SSam Ravnborg control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1212a88b5ba8SSam Ravnborg switch (tsbsize) {
1213a88b5ba8SSam Ravnborg case 64:
1214a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_TSBSZ_64K;
1215a88b5ba8SSam Ravnborg break;
1216a88b5ba8SSam Ravnborg case 128:
1217a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_TSBSZ_128K;
1218a88b5ba8SSam Ravnborg break;
1219a88b5ba8SSam Ravnborg }
1220a88b5ba8SSam Ravnborg
1221a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_CTRL_ENAB;
1222a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control);
1223a88b5ba8SSam Ravnborg
1224a88b5ba8SSam Ravnborg return 0;
1225a88b5ba8SSam Ravnborg }
1226a88b5ba8SSam Ravnborg
1227a88b5ba8SSam Ravnborg #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1228a88b5ba8SSam Ravnborg #define SCHIZO_IRQ_RETRY_INF 0xffUL
1229a88b5ba8SSam Ravnborg
1230a88b5ba8SSam Ravnborg #define SCHIZO_PCI_DIAG (0x2020UL)
1231a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1232a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1233a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1234a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1235a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1236a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1237a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1238a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1239a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1240a88b5ba8SSam Ravnborg
1241a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1242a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1243a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1244a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1245a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1246a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1247a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1248a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1249a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1250a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1251a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1252a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1253a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1254a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1255a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1256a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1257a88b5ba8SSam Ravnborg
1258a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1259a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1260a88b5ba8SSam Ravnborg
schizo_pbm_hw_init(struct pci_pbm_info * pbm)1261a88b5ba8SSam Ravnborg static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1262a88b5ba8SSam Ravnborg {
1263a88b5ba8SSam Ravnborg u64 tmp;
1264a88b5ba8SSam Ravnborg
1265a88b5ba8SSam Ravnborg upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1266a88b5ba8SSam Ravnborg
1267a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1268a88b5ba8SSam Ravnborg
1269a88b5ba8SSam Ravnborg /* Enable arbiter for all PCI slots. */
1270a88b5ba8SSam Ravnborg tmp |= 0xff;
1271a88b5ba8SSam Ravnborg
1272a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1273a88b5ba8SSam Ravnborg pbm->chip_version >= 0x2)
1274a88b5ba8SSam Ravnborg tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1275a88b5ba8SSam Ravnborg
1276928f4de0SRob Herring if (!of_property_read_bool(pbm->op->dev.of_node, "no-bus-parking"))
1277a88b5ba8SSam Ravnborg tmp |= SCHIZO_PCICTRL_PARK;
1278a88b5ba8SSam Ravnborg else
1279a88b5ba8SSam Ravnborg tmp &= ~SCHIZO_PCICTRL_PARK;
1280a88b5ba8SSam Ravnborg
1281a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1282a88b5ba8SSam Ravnborg pbm->chip_version <= 0x1)
1283a88b5ba8SSam Ravnborg tmp |= SCHIZO_PCICTRL_DTO_INT;
1284a88b5ba8SSam Ravnborg else
1285a88b5ba8SSam Ravnborg tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1286a88b5ba8SSam Ravnborg
1287a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1288a88b5ba8SSam Ravnborg tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1289a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RDO_PREF |
1290a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RDL_PREF);
1291a88b5ba8SSam Ravnborg
1292a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1293a88b5ba8SSam Ravnborg
1294a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1295a88b5ba8SSam Ravnborg tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1296a88b5ba8SSam Ravnborg SCHIZO_PCIDIAG_D_RETRY |
1297a88b5ba8SSam Ravnborg SCHIZO_PCIDIAG_D_INTSYNC);
1298a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1299a88b5ba8SSam Ravnborg
1300a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1301a88b5ba8SSam Ravnborg /* Clear prefetch lengths to workaround a bug in
1302a88b5ba8SSam Ravnborg * Jalapeno...
1303a88b5ba8SSam Ravnborg */
1304a88b5ba8SSam Ravnborg tmp = (TOMATILLO_IOC_PART_WPENAB |
1305a88b5ba8SSam Ravnborg (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1306a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDMULT_CPENAB |
1307a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDONE_CPENAB |
1308a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDLINE_CPENAB);
1309a88b5ba8SSam Ravnborg
1310a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1311a88b5ba8SSam Ravnborg }
1312a88b5ba8SSam Ravnborg }
1313a88b5ba8SSam Ravnborg
schizo_pbm_init(struct pci_pbm_info * pbm,struct platform_device * op,u32 portid,int chip_type)1314b7c13f76SSam Ravnborg static int schizo_pbm_init(struct pci_pbm_info *pbm,
1315cd4cd730SGrant Likely struct platform_device *op, u32 portid,
1316a88b5ba8SSam Ravnborg int chip_type)
1317a88b5ba8SSam Ravnborg {
1318a88b5ba8SSam Ravnborg const struct linux_prom64_registers *regs;
131961c7a080SGrant Likely struct device_node *dp = op->dev.of_node;
1320a88b5ba8SSam Ravnborg const char *chipset_name;
1321c6fee081SDavid S. Miller int err;
1322a88b5ba8SSam Ravnborg
1323a88b5ba8SSam Ravnborg switch (chip_type) {
1324a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_TOMATILLO:
1325a88b5ba8SSam Ravnborg chipset_name = "TOMATILLO";
1326a88b5ba8SSam Ravnborg break;
1327a88b5ba8SSam Ravnborg
1328a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_SCHIZO_PLUS:
1329a88b5ba8SSam Ravnborg chipset_name = "SCHIZO+";
1330a88b5ba8SSam Ravnborg break;
1331a88b5ba8SSam Ravnborg
1332a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_SCHIZO:
1333a88b5ba8SSam Ravnborg default:
1334a88b5ba8SSam Ravnborg chipset_name = "SCHIZO";
1335a88b5ba8SSam Ravnborg break;
13366cb79b3fSJoe Perches }
1337a88b5ba8SSam Ravnborg
1338a88b5ba8SSam Ravnborg /* For SCHIZO, three OBP regs:
1339a88b5ba8SSam Ravnborg * 1) PBM controller regs
1340a88b5ba8SSam Ravnborg * 2) Schizo front-end controller regs (same for both PBMs)
1341a88b5ba8SSam Ravnborg * 3) PBM PCI config space
1342a88b5ba8SSam Ravnborg *
1343a88b5ba8SSam Ravnborg * For TOMATILLO, four OBP regs:
1344a88b5ba8SSam Ravnborg * 1) PBM controller regs
1345a88b5ba8SSam Ravnborg * 2) Tomatillo front-end controller regs
1346a88b5ba8SSam Ravnborg * 3) PBM PCI config space
1347a88b5ba8SSam Ravnborg * 4) Ichip regs
1348a88b5ba8SSam Ravnborg */
1349a88b5ba8SSam Ravnborg regs = of_get_property(dp, "reg", NULL);
1350a88b5ba8SSam Ravnborg
1351a88b5ba8SSam Ravnborg pbm->next = pci_pbm_root;
1352a88b5ba8SSam Ravnborg pci_pbm_root = pbm;
1353a88b5ba8SSam Ravnborg
135498fa15f3SAnshuman Khandual pbm->numa_node = NUMA_NO_NODE;
1355a88b5ba8SSam Ravnborg
1356a88b5ba8SSam Ravnborg pbm->pci_ops = &sun4u_pci_ops;
1357a88b5ba8SSam Ravnborg pbm->config_space_reg_bits = 8;
1358a88b5ba8SSam Ravnborg
1359a88b5ba8SSam Ravnborg pbm->index = pci_num_pbms++;
1360a88b5ba8SSam Ravnborg
1361a88b5ba8SSam Ravnborg pbm->portid = portid;
1362a88b5ba8SSam Ravnborg pbm->op = op;
1363a88b5ba8SSam Ravnborg
1364a88b5ba8SSam Ravnborg pbm->chip_type = chip_type;
1365a88b5ba8SSam Ravnborg pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1366a88b5ba8SSam Ravnborg pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1367a88b5ba8SSam Ravnborg
1368a88b5ba8SSam Ravnborg pbm->pbm_regs = regs[0].phys_addr;
1369a88b5ba8SSam Ravnborg pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1370a88b5ba8SSam Ravnborg
1371a88b5ba8SSam Ravnborg if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1372a88b5ba8SSam Ravnborg pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1373a88b5ba8SSam Ravnborg
1374a88b5ba8SSam Ravnborg pbm->name = dp->full_name;
1375a88b5ba8SSam Ravnborg
1376a88b5ba8SSam Ravnborg printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1377a88b5ba8SSam Ravnborg pbm->name, chipset_name,
1378a88b5ba8SSam Ravnborg pbm->chip_version, pbm->chip_revision);
1379a88b5ba8SSam Ravnborg
1380a88b5ba8SSam Ravnborg schizo_pbm_hw_init(pbm);
1381a88b5ba8SSam Ravnborg
1382a88b5ba8SSam Ravnborg pci_determine_mem_io_space(pbm);
1383a88b5ba8SSam Ravnborg
1384a88b5ba8SSam Ravnborg pci_get_pbm_props(pbm);
1385a88b5ba8SSam Ravnborg
1386a88b5ba8SSam Ravnborg err = schizo_pbm_iommu_init(pbm);
1387a88b5ba8SSam Ravnborg if (err)
1388a88b5ba8SSam Ravnborg return err;
1389a88b5ba8SSam Ravnborg
1390a88b5ba8SSam Ravnborg schizo_pbm_strbuf_init(pbm);
1391a88b5ba8SSam Ravnborg
1392a88b5ba8SSam Ravnborg schizo_scan_bus(pbm, &op->dev);
1393a88b5ba8SSam Ravnborg
1394a88b5ba8SSam Ravnborg return 0;
1395a88b5ba8SSam Ravnborg }
1396a88b5ba8SSam Ravnborg
portid_compare(u32 x,u32 y,int chip_type)1397a88b5ba8SSam Ravnborg static inline int portid_compare(u32 x, u32 y, int chip_type)
1398a88b5ba8SSam Ravnborg {
1399a88b5ba8SSam Ravnborg if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1400a88b5ba8SSam Ravnborg if (x == (y ^ 1))
1401a88b5ba8SSam Ravnborg return 1;
1402a88b5ba8SSam Ravnborg return 0;
1403a88b5ba8SSam Ravnborg }
1404a88b5ba8SSam Ravnborg return (x == y);
1405a88b5ba8SSam Ravnborg }
1406a88b5ba8SSam Ravnborg
schizo_find_sibling(u32 portid,int chip_type)1407b7c13f76SSam Ravnborg static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type)
1408a88b5ba8SSam Ravnborg {
1409a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm;
1410a88b5ba8SSam Ravnborg
1411a88b5ba8SSam Ravnborg for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1412a88b5ba8SSam Ravnborg if (portid_compare(pbm->portid, portid, chip_type))
1413a88b5ba8SSam Ravnborg return pbm;
1414a88b5ba8SSam Ravnborg }
1415a88b5ba8SSam Ravnborg return NULL;
1416a88b5ba8SSam Ravnborg }
1417a88b5ba8SSam Ravnborg
__schizo_init(struct platform_device * op,unsigned long chip_type)1418b7c13f76SSam Ravnborg static int __schizo_init(struct platform_device *op, unsigned long chip_type)
1419a88b5ba8SSam Ravnborg {
142061c7a080SGrant Likely struct device_node *dp = op->dev.of_node;
1421a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm;
1422a88b5ba8SSam Ravnborg struct iommu *iommu;
1423a88b5ba8SSam Ravnborg u32 portid;
1424a88b5ba8SSam Ravnborg int err;
1425a88b5ba8SSam Ravnborg
1426a88b5ba8SSam Ravnborg portid = of_getintprop_default(dp, "portid", 0xff);
1427a88b5ba8SSam Ravnborg
1428a88b5ba8SSam Ravnborg err = -ENOMEM;
1429a88b5ba8SSam Ravnborg pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1430a88b5ba8SSam Ravnborg if (!pbm) {
1431a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
1432a88b5ba8SSam Ravnborg goto out_err;
1433a88b5ba8SSam Ravnborg }
1434a88b5ba8SSam Ravnborg
1435a88b5ba8SSam Ravnborg pbm->sibling = schizo_find_sibling(portid, chip_type);
1436a88b5ba8SSam Ravnborg
1437a88b5ba8SSam Ravnborg iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1438a88b5ba8SSam Ravnborg if (!iommu) {
1439a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1440a88b5ba8SSam Ravnborg goto out_free_pbm;
1441a88b5ba8SSam Ravnborg }
1442a88b5ba8SSam Ravnborg
1443a88b5ba8SSam Ravnborg pbm->iommu = iommu;
1444a88b5ba8SSam Ravnborg
1445a88b5ba8SSam Ravnborg if (schizo_pbm_init(pbm, op, portid, chip_type))
1446a88b5ba8SSam Ravnborg goto out_free_iommu;
1447a88b5ba8SSam Ravnborg
1448a88b5ba8SSam Ravnborg if (pbm->sibling)
1449a88b5ba8SSam Ravnborg pbm->sibling->sibling = pbm;
1450a88b5ba8SSam Ravnborg
1451a88b5ba8SSam Ravnborg dev_set_drvdata(&op->dev, pbm);
1452a88b5ba8SSam Ravnborg
1453a88b5ba8SSam Ravnborg return 0;
1454a88b5ba8SSam Ravnborg
1455a88b5ba8SSam Ravnborg out_free_iommu:
1456a88b5ba8SSam Ravnborg kfree(pbm->iommu);
1457a88b5ba8SSam Ravnborg
1458a88b5ba8SSam Ravnborg out_free_pbm:
1459a88b5ba8SSam Ravnborg kfree(pbm);
1460a88b5ba8SSam Ravnborg
1461a88b5ba8SSam Ravnborg out_err:
1462a88b5ba8SSam Ravnborg return err;
1463a88b5ba8SSam Ravnborg }
1464a88b5ba8SSam Ravnborg
schizo_probe(struct platform_device * op)1465b7c13f76SSam Ravnborg static int schizo_probe(struct platform_device *op)
1466a88b5ba8SSam Ravnborg {
146761c2ef4bSRob Herring unsigned long chip_type = (unsigned long)device_get_match_data(&op->dev);
1468b1608d69SGrant Likely
146961c2ef4bSRob Herring if (!chip_type)
14704ebb24f7SGrant Likely return -EINVAL;
147161c2ef4bSRob Herring return __schizo_init(op, chip_type);
1472a88b5ba8SSam Ravnborg }
1473a88b5ba8SSam Ravnborg
1474a88b5ba8SSam Ravnborg /* The ordering of this table is very important. Some Tomatillo
1475a88b5ba8SSam Ravnborg * nodes announce that they are compatible with both pci108e,a801
1476a88b5ba8SSam Ravnborg * and pci108e,8001. So list the chips in reverse chronological
1477a88b5ba8SSam Ravnborg * order.
1478a88b5ba8SSam Ravnborg */
14793628aa06SDavid S. Miller static const struct of_device_id schizo_match[] = {
1480a88b5ba8SSam Ravnborg {
1481a88b5ba8SSam Ravnborg .name = "pci",
1482a88b5ba8SSam Ravnborg .compatible = "pci108e,a801",
1483a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1484a88b5ba8SSam Ravnborg },
1485a88b5ba8SSam Ravnborg {
1486a88b5ba8SSam Ravnborg .name = "pci",
1487a88b5ba8SSam Ravnborg .compatible = "pci108e,8002",
1488a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1489a88b5ba8SSam Ravnborg },
1490a88b5ba8SSam Ravnborg {
1491a88b5ba8SSam Ravnborg .name = "pci",
1492a88b5ba8SSam Ravnborg .compatible = "pci108e,8001",
1493a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1494a88b5ba8SSam Ravnborg },
1495a88b5ba8SSam Ravnborg {},
1496a88b5ba8SSam Ravnborg };
1497a88b5ba8SSam Ravnborg
14984ebb24f7SGrant Likely static struct platform_driver schizo_driver = {
14994018294bSGrant Likely .driver = {
1500a88b5ba8SSam Ravnborg .name = DRIVER_NAME,
15014018294bSGrant Likely .of_match_table = schizo_match,
15024018294bSGrant Likely },
1503a88b5ba8SSam Ravnborg .probe = schizo_probe,
1504a88b5ba8SSam Ravnborg };
1505a88b5ba8SSam Ravnborg
schizo_init(void)1506a88b5ba8SSam Ravnborg static int __init schizo_init(void)
1507a88b5ba8SSam Ravnborg {
15084ebb24f7SGrant Likely return platform_driver_register(&schizo_driver);
1509a88b5ba8SSam Ravnborg }
1510a88b5ba8SSam Ravnborg
1511a88b5ba8SSam Ravnborg subsys_initcall(schizo_init);
1512