1ff61f079SJonathan Corbet================= 2ff61f079SJonathan Corbetx86 IOMMU Support 3ff61f079SJonathan Corbet================= 4ff61f079SJonathan Corbet 5ff61f079SJonathan CorbetThe architecture specs can be obtained from the below locations. 6ff61f079SJonathan Corbet 7ff61f079SJonathan Corbet- Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf 8*c53cbc54SJianlin Li- AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_07_PUB.pdf 9ff61f079SJonathan Corbet 10ff61f079SJonathan CorbetThis guide gives a quick cheat sheet for some basic understanding. 11ff61f079SJonathan Corbet 12ff61f079SJonathan CorbetBasic stuff 13ff61f079SJonathan Corbet----------- 14ff61f079SJonathan Corbet 15ff61f079SJonathan CorbetACPI enumerates and lists the different IOMMUs on the platform, and 16ff61f079SJonathan Corbetdevice scope relationships between devices and which IOMMU controls 17ff61f079SJonathan Corbetthem. 18ff61f079SJonathan Corbet 19ff61f079SJonathan CorbetSome ACPI Keywords: 20ff61f079SJonathan Corbet 21ff61f079SJonathan Corbet- DMAR - Intel DMA Remapping table 22ff61f079SJonathan Corbet- DRHD - Intel DMA Remapping Hardware Unit Definition 23ff61f079SJonathan Corbet- RMRR - Intel Reserved Memory Region Reporting Structure 24ff61f079SJonathan Corbet- IVRS - AMD I/O Virtualization Reporting Structure 25ff61f079SJonathan Corbet- IVDB - AMD I/O Virtualization Definition Block 26ff61f079SJonathan Corbet- IVHD - AMD I/O Virtualization Hardware Definition 27ff61f079SJonathan Corbet 28ff61f079SJonathan CorbetWhat is Intel RMRR? 29ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^^ 30ff61f079SJonathan Corbet 31ff61f079SJonathan CorbetThere are some devices the BIOS controls, for e.g USB devices to perform 32ff61f079SJonathan CorbetPS2 emulation. The regions of memory used for these devices are marked 33ff61f079SJonathan Corbetreserved in the e820 map. When we turn on DMA translation, DMA to those 34ff61f079SJonathan Corbetregions will fail. Hence BIOS uses RMRR to specify these regions along with 35ff61f079SJonathan Corbetdevices that need to access these regions. OS is expected to setup 36ff61f079SJonathan Corbetunity mappings for these regions for these devices to access these regions. 37ff61f079SJonathan Corbet 38ff61f079SJonathan CorbetWhat is AMD IVRS? 39ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^ 40ff61f079SJonathan Corbet 41ff61f079SJonathan CorbetThe architecture defines an ACPI-compatible data structure called an I/O 42ff61f079SJonathan CorbetVirtualization Reporting Structure (IVRS) that is used to convey information 43ff61f079SJonathan Corbetrelated to I/O virtualization to system software. The IVRS describes the 44ff61f079SJonathan Corbetconfiguration and capabilities of the IOMMUs contained in the platform as 45ff61f079SJonathan Corbetwell as information about the devices that each IOMMU virtualizes. 46ff61f079SJonathan Corbet 47ff61f079SJonathan CorbetThe IVRS provides information about the following: 48ff61f079SJonathan Corbet 49ff61f079SJonathan Corbet- IOMMUs present in the platform including their capabilities and proper configuration 50ff61f079SJonathan Corbet- System I/O topology relevant to each IOMMU 51ff61f079SJonathan Corbet- Peripheral devices that cannot be otherwise enumerated 52ff61f079SJonathan Corbet- Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are generally exclusion ranges to be configured by system software. 53ff61f079SJonathan Corbet 54ff61f079SJonathan CorbetHow is an I/O Virtual Address (IOVA) generated? 55ff61f079SJonathan Corbet----------------------------------------------- 56ff61f079SJonathan Corbet 57ff61f079SJonathan CorbetWell behaved drivers call dma_map_*() calls before sending command to device 58ff61f079SJonathan Corbetthat needs to perform DMA. Once DMA is completed and mapping is no longer 59ff61f079SJonathan Corbetrequired, driver performs dma_unmap_*() calls to unmap the region. 60ff61f079SJonathan Corbet 61ff61f079SJonathan CorbetIntel Specific Notes 62ff61f079SJonathan Corbet-------------------- 63ff61f079SJonathan Corbet 64ff61f079SJonathan CorbetGraphics Problems? 65ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^ 66ff61f079SJonathan Corbet 67ff61f079SJonathan CorbetIf you encounter issues with graphics devices, you can try adding 68ff61f079SJonathan Corbetoption intel_iommu=igfx_off to turn off the integrated graphics engine. 69ff61f079SJonathan CorbetIf this fixes anything, please ensure you file a bug reporting the problem. 70ff61f079SJonathan Corbet 71ff61f079SJonathan CorbetSome exceptions to IOVA 72ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^^^^^^ 73ff61f079SJonathan Corbet 74ff61f079SJonathan CorbetInterrupt ranges are not address translated, (0xfee00000 - 0xfeefffff). 75ff61f079SJonathan CorbetThe same is true for peer to peer transactions. Hence we reserve the 76ff61f079SJonathan Corbetaddress from PCI MMIO ranges so they are not allocated for IOVA addresses. 77ff61f079SJonathan Corbet 78ff61f079SJonathan CorbetAMD Specific Notes 79ff61f079SJonathan Corbet------------------ 80ff61f079SJonathan Corbet 81ff61f079SJonathan CorbetGraphics Problems? 82ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^ 83ff61f079SJonathan Corbet 84ff61f079SJonathan CorbetIf you encounter issues with integrated graphics devices, you can try adding 85ff61f079SJonathan Corbetoption iommu=pt to the kernel command line use a 1:1 mapping for the IOMMU. If 86ff61f079SJonathan Corbetthis fixes anything, please ensure you file a bug reporting the problem. 87ff61f079SJonathan Corbet 88ff61f079SJonathan CorbetFault reporting 89ff61f079SJonathan Corbet--------------- 90ff61f079SJonathan CorbetWhen errors are reported, the IOMMU signals via an interrupt. The fault 91ff61f079SJonathan Corbetreason and device that caused it is printed on the console. 92ff61f079SJonathan Corbet 93ff61f079SJonathan Corbet 94ff61f079SJonathan CorbetKernel Log Samples 95ff61f079SJonathan Corbet------------------ 96ff61f079SJonathan Corbet 97ff61f079SJonathan CorbetIntel Boot Messages 98ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^^ 99ff61f079SJonathan Corbet 100ff61f079SJonathan CorbetSomething like this gets printed indicating presence of DMAR tables 101ff61f079SJonathan Corbetin ACPI: 102ff61f079SJonathan Corbet 103ff61f079SJonathan Corbet:: 104ff61f079SJonathan Corbet 105ff61f079SJonathan Corbet ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0 106ff61f079SJonathan Corbet 107ff61f079SJonathan CorbetWhen DMAR is being processed and initialized by ACPI, prints DMAR locations 108ff61f079SJonathan Corbetand any RMRR's processed: 109ff61f079SJonathan Corbet 110ff61f079SJonathan Corbet:: 111ff61f079SJonathan Corbet 112ff61f079SJonathan Corbet ACPI DMAR:Host address width 36 113ff61f079SJonathan Corbet ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000 114ff61f079SJonathan Corbet ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000 115ff61f079SJonathan Corbet ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000 116ff61f079SJonathan Corbet ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff 117ff61f079SJonathan Corbet ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff 118ff61f079SJonathan Corbet 119ff61f079SJonathan CorbetWhen DMAR is enabled for use, you will notice: 120ff61f079SJonathan Corbet 121ff61f079SJonathan Corbet:: 122ff61f079SJonathan Corbet 123ff61f079SJonathan Corbet PCI-DMA: Using DMAR IOMMU 124ff61f079SJonathan Corbet 125ff61f079SJonathan CorbetIntel Fault reporting 126ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^^^^ 127ff61f079SJonathan Corbet 128ff61f079SJonathan Corbet:: 129ff61f079SJonathan Corbet 130ff61f079SJonathan Corbet DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 131ff61f079SJonathan Corbet DMAR:[fault reason 05] PTE Write access is not set 132ff61f079SJonathan Corbet DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 133ff61f079SJonathan Corbet DMAR:[fault reason 05] PTE Write access is not set 134ff61f079SJonathan Corbet 135ff61f079SJonathan CorbetAMD Boot Messages 136ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^ 137ff61f079SJonathan Corbet 138ff61f079SJonathan CorbetSomething like this gets printed indicating presence of the IOMMU: 139ff61f079SJonathan Corbet 140ff61f079SJonathan Corbet:: 141ff61f079SJonathan Corbet 142ff61f079SJonathan Corbet iommu: Default domain type: Translated 143ff61f079SJonathan Corbet iommu: DMA domain TLB invalidation policy: lazy mode 144ff61f079SJonathan Corbet 145ff61f079SJonathan CorbetAMD Fault reporting 146ff61f079SJonathan Corbet^^^^^^^^^^^^^^^^^^^ 147ff61f079SJonathan Corbet 148ff61f079SJonathan Corbet:: 149ff61f079SJonathan Corbet 150ff61f079SJonathan Corbet AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000] 151ff61f079SJonathan Corbet AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000] 152