1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_fire.c: Sun4u platform PCI-E controller support.
7 #include <linux/pci.h>
33 	struct iommu *iommu = pbm->iommu;  in pci_fire_pbm_iommu_init()  local
38 	/* No virtual-dma property on these guys, use largest size.  */  in pci_fire_pbm_iommu_init()
45 	iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;  in pci_fire_pbm_iommu_init()
46 	iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;  in pci_fire_pbm_iommu_init()
47 	iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;  in pci_fire_pbm_iommu_init()
48 	iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;  in pci_fire_pbm_iommu_init()
53 	iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;  in pci_fire_pbm_iommu_init()
58 	upa_writeq(~(u64)0, iommu->iommu_flushinv);  in pci_fire_pbm_iommu_init()
60 	err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,  in pci_fire_pbm_iommu_init()
61 			       pbm->numa_node);  in pci_fire_pbm_iommu_init()
65 	upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);  in pci_fire_pbm_iommu_init()
67 	control = upa_readq(iommu->iommu_control);  in pci_fire_pbm_iommu_init()
72 	upa_writeq(control, iommu->iommu_control);  in pci_fire_pbm_iommu_init()
105 /* All MSI registers are offset from pbm->pbm_regs */
154 	*head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));  in pci_fire_get_head()
164 	base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));  in pci_fire_dequeue_msi()
167 	if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)  in pci_fire_dequeue_msi()
170 	type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>  in pci_fire_dequeue_msi()
175 		return -EINVAL;  in pci_fire_dequeue_msi()
177 	*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>  in pci_fire_dequeue_msi()
180 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));  in pci_fire_dequeue_msi()
183 	ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;  in pci_fire_dequeue_msi()
187 	if (*head >= pbm->msiq_ent_count)  in pci_fire_dequeue_msi()
196 	upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));  in pci_fire_set_head()
205 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
208 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
210 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));  in pci_fire_msi_setup()
212 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
214 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
223 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_teardown()
227 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_teardown()
241 		return -ENOMEM;  in pci_fire_msiq_alloc()
244 	pbm->msi_queues = (void *) pages;  in pci_fire_msiq_alloc()
247 		    __pa(pbm->msi_queues)),  in pci_fire_msiq_alloc()
248 		   pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);  in pci_fire_msiq_alloc()
250 	upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);  in pci_fire_msiq_alloc()
251 	upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);  in pci_fire_msiq_alloc()
253 	upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);  in pci_fire_msiq_alloc()
254 	upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);  in pci_fire_msiq_alloc()
256 	for (i = 0; i < pbm->msiq_num; i++) {  in pci_fire_msiq_alloc()
257 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));  in pci_fire_msiq_alloc()
258 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));  in pci_fire_msiq_alloc()
269 	pages = (unsigned long) pbm->msi_queues;  in pci_fire_msiq_free()
273 	pbm->msi_queues = NULL;  in pci_fire_msiq_free()
280 	unsigned long cregs = (unsigned long) pbm->pbm_regs;  in pci_fire_msiq_build_irq()
296 	fixup = ((pbm->portid << 6) | devino) - int_ctrlr;  in pci_fire_msiq_build_irq()
300 		return -ENOMEM;  in pci_fire_msiq_build_irq()
303 		   pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));  in pci_fire_msiq_build_irq()
329 /* Based at pbm->controller_regs */
343 /* Based at pbm->pbm_regs */
372 		   pbm->controller_regs + FIRE_PARITY_CONTROL);  in pci_fire_hw_init()
382 		   pbm->controller_regs + FIRE_FATAL_RESET_CTL);  in pci_fire_hw_init()
384 	upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);  in pci_fire_hw_init()
386 	val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);  in pci_fire_hw_init()
390 	upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);  in pci_fire_hw_init()
391 	upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);  in pci_fire_hw_init()
393 		   pbm->pbm_regs + FIRE_TLU_LINK_CTRL);  in pci_fire_hw_init()
395 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);  in pci_fire_hw_init()
396 	upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);  in pci_fire_hw_init()
398 		   pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);  in pci_fire_hw_init()
400 		   pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);  in pci_fire_hw_init()
401 	upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);  in pci_fire_hw_init()
402 	upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);  in pci_fire_hw_init()
404 		   pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);  in pci_fire_hw_init()
405 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);  in pci_fire_hw_init()
407 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);  in pci_fire_hw_init()
408 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);  in pci_fire_hw_init()
409 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);  in pci_fire_hw_init()
411 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);  in pci_fire_hw_init()
418 	struct device_node *dp = op->dev.of_node;  in pci_fire_pbm_init()
421 	pbm->numa_node = NUMA_NO_NODE;  in pci_fire_pbm_init()
423 	pbm->pci_ops = &sun4u_pci_ops;  in pci_fire_pbm_init()
424 	pbm->config_space_reg_bits = 12;  in pci_fire_pbm_init()
426 	pbm->index = pci_num_pbms++;  in pci_fire_pbm_init()
428 	pbm->portid = portid;  in pci_fire_pbm_init()
429 	pbm->op = op;  in pci_fire_pbm_init()
430 	pbm->name = dp->full_name;  in pci_fire_pbm_init()
433 	pbm->pbm_regs = regs[0].phys_addr;  in pci_fire_pbm_init()
434 	pbm->controller_regs = regs[1].phys_addr - 0x410000UL;  in pci_fire_pbm_init()
436 	printk("%s: SUN4U PCIE Bus Module\n", pbm->name);  in pci_fire_pbm_init()
450 	pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);  in pci_fire_pbm_init()
454 	pbm->next = pci_pbm_root;  in pci_fire_pbm_init()
462 	struct device_node *dp = op->dev.of_node;  in fire_probe()
464 	struct iommu *iommu;  in fire_probe()  local
470 	err = -ENOMEM;  in fire_probe()
477 	iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);  in fire_probe()
478 	if (!iommu) {  in fire_probe()
479 		printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");  in fire_probe()
483 	pbm->iommu = iommu;  in fire_probe()
489 	dev_set_drvdata(&op->dev, pbm);  in fire_probe()
494 	kfree(pbm->iommu);  in fire_probe()
505 		.name = "pci",