Lines Matching +full:pci +full:- +full:iommu

2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
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16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
26 - IVHD - AMD I/O Virtualization Hardware Definition
41 The architecture defines an ACPI-compatible data structure called an I/O
45 well as information about the devices that each IOMMU virtualizes.
49 - IOMMUs present in the platform including their capabilities and proper configuration
50 - System I/O topology relevant to each IOMMU
51 - Peripheral devices that cannot be otherwise enumerated
52 - Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are generally exc…
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74 Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
76 address from PCI MMIO ranges so they are not allocated for IOVA addresses.
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85 option iommu=pt to the kernel command line use a 1:1 mapping for the IOMMU.  If
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90 When errors are reported, the IOMMU signals via an interrupt. The fault
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123 	PCI-DMA: Using DMAR IOMMU
138 Something like this gets printed indicating presence of the IOMMU:
142 	iommu: Default domain type: Translated
143 	iommu: DMA domain TLB invalidation policy: lazy mode
150 	AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000]
151 	AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000]