xref: /linux/Documentation/arch/x86/x86_64/boot-options.rst (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1*ff61f079SJonathan Corbet.. SPDX-License-Identifier: GPL-2.0
2*ff61f079SJonathan Corbet
3*ff61f079SJonathan Corbet===========================
4*ff61f079SJonathan CorbetAMD64 Specific Boot Options
5*ff61f079SJonathan Corbet===========================
6*ff61f079SJonathan Corbet
7*ff61f079SJonathan CorbetThere are many others (usually documented in driver documentation), but
8*ff61f079SJonathan Corbetonly the AMD64 specific ones are listed here.
9*ff61f079SJonathan Corbet
10*ff61f079SJonathan CorbetMachine check
11*ff61f079SJonathan Corbet=============
12*ff61f079SJonathan CorbetPlease see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
13*ff61f079SJonathan Corbet
14*ff61f079SJonathan Corbet   mce=off
15*ff61f079SJonathan Corbet		Disable machine check
16*ff61f079SJonathan Corbet   mce=no_cmci
17*ff61f079SJonathan Corbet		Disable CMCI(Corrected Machine Check Interrupt) that
18*ff61f079SJonathan Corbet		Intel processor supports.  Usually this disablement is
19*ff61f079SJonathan Corbet		not recommended, but it might be handy if your hardware
20*ff61f079SJonathan Corbet		is misbehaving.
21*ff61f079SJonathan Corbet		Note that you'll get more problems without CMCI than with
22*ff61f079SJonathan Corbet		due to the shared banks, i.e. you might get duplicated
23*ff61f079SJonathan Corbet		error logs.
24*ff61f079SJonathan Corbet   mce=dont_log_ce
25*ff61f079SJonathan Corbet		Don't make logs for corrected errors.  All events reported
26*ff61f079SJonathan Corbet		as corrected are silently cleared by OS.
27*ff61f079SJonathan Corbet		This option will be useful if you have no interest in any
28*ff61f079SJonathan Corbet		of corrected errors.
29*ff61f079SJonathan Corbet   mce=ignore_ce
30*ff61f079SJonathan Corbet		Disable features for corrected errors, e.g. polling timer
31*ff61f079SJonathan Corbet		and CMCI.  All events reported as corrected are not cleared
32*ff61f079SJonathan Corbet		by OS and remained in its error banks.
33*ff61f079SJonathan Corbet		Usually this disablement is not recommended, however if
34*ff61f079SJonathan Corbet		there is an agent checking/clearing corrected errors
35*ff61f079SJonathan Corbet		(e.g. BIOS or hardware monitoring applications), conflicting
36*ff61f079SJonathan Corbet		with OS's error handling, and you cannot deactivate the agent,
37*ff61f079SJonathan Corbet		then this option will be a help.
38*ff61f079SJonathan Corbet   mce=no_lmce
39*ff61f079SJonathan Corbet		Do not opt-in to Local MCE delivery. Use legacy method
40*ff61f079SJonathan Corbet		to broadcast MCEs.
41*ff61f079SJonathan Corbet   mce=bootlog
42*ff61f079SJonathan Corbet		Enable logging of machine checks left over from booting.
43*ff61f079SJonathan Corbet		Disabled by default on AMD Fam10h and older because some BIOS
44*ff61f079SJonathan Corbet		leave bogus ones.
45*ff61f079SJonathan Corbet		If your BIOS doesn't do that it's a good idea to enable though
46*ff61f079SJonathan Corbet		to make sure you log even machine check events that result
47*ff61f079SJonathan Corbet		in a reboot. On Intel systems it is enabled by default.
48*ff61f079SJonathan Corbet   mce=nobootlog
49*ff61f079SJonathan Corbet		Disable boot machine check logging.
50*ff61f079SJonathan Corbet   mce=monarchtimeout (number)
51*ff61f079SJonathan Corbet		monarchtimeout:
52*ff61f079SJonathan Corbet		Sets the time in us to wait for other CPUs on machine checks. 0
53*ff61f079SJonathan Corbet		to disable.
54*ff61f079SJonathan Corbet   mce=bios_cmci_threshold
55*ff61f079SJonathan Corbet		Don't overwrite the bios-set CMCI threshold. This boot option
56*ff61f079SJonathan Corbet		prevents Linux from overwriting the CMCI threshold set by the
57*ff61f079SJonathan Corbet		bios. Without this option, Linux always sets the CMCI
58*ff61f079SJonathan Corbet		threshold to 1. Enabling this may make memory predictive failure
59*ff61f079SJonathan Corbet		analysis less effective if the bios sets thresholds for memory
60*ff61f079SJonathan Corbet		errors since we will not see details for all errors.
61*ff61f079SJonathan Corbet   mce=recovery
62*ff61f079SJonathan Corbet		Force-enable recoverable machine check code paths
63*ff61f079SJonathan Corbet
64*ff61f079SJonathan Corbet   nomce (for compatibility with i386)
65*ff61f079SJonathan Corbet		same as mce=off
66*ff61f079SJonathan Corbet
67*ff61f079SJonathan Corbet   Everything else is in sysfs now.
68*ff61f079SJonathan Corbet
69*ff61f079SJonathan CorbetAPICs
70*ff61f079SJonathan Corbet=====
71*ff61f079SJonathan Corbet
72*ff61f079SJonathan Corbet   apic
73*ff61f079SJonathan Corbet	Use IO-APIC. Default
74*ff61f079SJonathan Corbet
75*ff61f079SJonathan Corbet   noapic
76*ff61f079SJonathan Corbet	Don't use the IO-APIC.
77*ff61f079SJonathan Corbet
78*ff61f079SJonathan Corbet   disableapic
79*ff61f079SJonathan Corbet	Don't use the local APIC
80*ff61f079SJonathan Corbet
81*ff61f079SJonathan Corbet   nolapic
82*ff61f079SJonathan Corbet     Don't use the local APIC (alias for i386 compatibility)
83*ff61f079SJonathan Corbet
84*ff61f079SJonathan Corbet   pirq=...
85*ff61f079SJonathan Corbet	See Documentation/arch/x86/i386/IO-APIC.rst
86*ff61f079SJonathan Corbet
87*ff61f079SJonathan Corbet   noapictimer
88*ff61f079SJonathan Corbet	Don't set up the APIC timer
89*ff61f079SJonathan Corbet
90*ff61f079SJonathan Corbet   no_timer_check
91*ff61f079SJonathan Corbet	Don't check the IO-APIC timer. This can work around
92*ff61f079SJonathan Corbet	problems with incorrect timer initialization on some boards.
93*ff61f079SJonathan Corbet
94*ff61f079SJonathan Corbet   apicpmtimer
95*ff61f079SJonathan Corbet	Do APIC timer calibration using the pmtimer. Implies
96*ff61f079SJonathan Corbet	apicmaintimer. Useful when your PIT timer is totally broken.
97*ff61f079SJonathan Corbet
98*ff61f079SJonathan CorbetTiming
99*ff61f079SJonathan Corbet======
100*ff61f079SJonathan Corbet
101*ff61f079SJonathan Corbet  notsc
102*ff61f079SJonathan Corbet    Deprecated, use tsc=unstable instead.
103*ff61f079SJonathan Corbet
104*ff61f079SJonathan Corbet  nohpet
105*ff61f079SJonathan Corbet    Don't use the HPET timer.
106*ff61f079SJonathan Corbet
107*ff61f079SJonathan CorbetIdle loop
108*ff61f079SJonathan Corbet=========
109*ff61f079SJonathan Corbet
110*ff61f079SJonathan Corbet  idle=poll
111*ff61f079SJonathan Corbet    Don't do power saving in the idle loop using HLT, but poll for rescheduling
112*ff61f079SJonathan Corbet    event. This will make the CPUs eat a lot more power, but may be useful
113*ff61f079SJonathan Corbet    to get slightly better performance in multiprocessor benchmarks. It also
114*ff61f079SJonathan Corbet    makes some profiling using performance counters more accurate.
115*ff61f079SJonathan Corbet    Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
116*ff61f079SJonathan Corbet    CPUs) this option has no performance advantage over the normal idle loop.
117*ff61f079SJonathan Corbet    It may also interact badly with hyperthreading.
118*ff61f079SJonathan Corbet
119*ff61f079SJonathan CorbetRebooting
120*ff61f079SJonathan Corbet=========
121*ff61f079SJonathan Corbet
122*ff61f079SJonathan Corbet   reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm | [c]old]
123*ff61f079SJonathan Corbet      bios
124*ff61f079SJonathan Corbet        Use the CPU reboot vector for warm reset
125*ff61f079SJonathan Corbet      warm
126*ff61f079SJonathan Corbet        Don't set the cold reboot flag
127*ff61f079SJonathan Corbet      cold
128*ff61f079SJonathan Corbet        Set the cold reboot flag
129*ff61f079SJonathan Corbet      triple
130*ff61f079SJonathan Corbet        Force a triple fault (init)
131*ff61f079SJonathan Corbet      kbd
132*ff61f079SJonathan Corbet        Use the keyboard controller. cold reset (default)
133*ff61f079SJonathan Corbet      acpi
134*ff61f079SJonathan Corbet        Use the ACPI RESET_REG in the FADT. If ACPI is not configured or
135*ff61f079SJonathan Corbet        the ACPI reset does not work, the reboot path attempts the reset
136*ff61f079SJonathan Corbet        using the keyboard controller.
137*ff61f079SJonathan Corbet      efi
138*ff61f079SJonathan Corbet        Use efi reset_system runtime service. If EFI is not configured or
139*ff61f079SJonathan Corbet        the EFI reset does not work, the reboot path attempts the reset using
140*ff61f079SJonathan Corbet        the keyboard controller.
141*ff61f079SJonathan Corbet      pci
142*ff61f079SJonathan Corbet        Use a write to the PCI config space register 0xcf9 to trigger reboot.
143*ff61f079SJonathan Corbet
144*ff61f079SJonathan Corbet   Using warm reset will be much faster especially on big memory
145*ff61f079SJonathan Corbet   systems because the BIOS will not go through the memory check.
146*ff61f079SJonathan Corbet   Disadvantage is that not all hardware will be completely reinitialized
147*ff61f079SJonathan Corbet   on reboot so there may be boot problems on some systems.
148*ff61f079SJonathan Corbet
149*ff61f079SJonathan Corbet   reboot=force
150*ff61f079SJonathan Corbet     Don't stop other CPUs on reboot. This can make reboot more reliable
151*ff61f079SJonathan Corbet     in some cases.
152*ff61f079SJonathan Corbet
153*ff61f079SJonathan Corbet   reboot=default
154*ff61f079SJonathan Corbet     There are some built-in platform specific "quirks" - you may see:
155*ff61f079SJonathan Corbet     "reboot: <name> series board detected. Selecting <type> for reboots."
156*ff61f079SJonathan Corbet     In the case where you think the quirk is in error (e.g. you have
157*ff61f079SJonathan Corbet     newer BIOS, or newer board) using this option will ignore the built-in
158*ff61f079SJonathan Corbet     quirk table, and use the generic default reboot actions.
159*ff61f079SJonathan Corbet
160*ff61f079SJonathan CorbetNUMA
161*ff61f079SJonathan Corbet====
162*ff61f079SJonathan Corbet
163*ff61f079SJonathan Corbet  numa=off
164*ff61f079SJonathan Corbet    Only set up a single NUMA node spanning all memory.
165*ff61f079SJonathan Corbet
166*ff61f079SJonathan Corbet  numa=noacpi
167*ff61f079SJonathan Corbet    Don't parse the SRAT table for NUMA setup
168*ff61f079SJonathan Corbet
169*ff61f079SJonathan Corbet  numa=nohmat
170*ff61f079SJonathan Corbet    Don't parse the HMAT table for NUMA setup, or soft-reserved memory
171*ff61f079SJonathan Corbet    partitioning.
172*ff61f079SJonathan Corbet
173*ff61f079SJonathan CorbetACPI
174*ff61f079SJonathan Corbet====
175*ff61f079SJonathan Corbet
176*ff61f079SJonathan Corbet  acpi=off
177*ff61f079SJonathan Corbet    Don't enable ACPI
178*ff61f079SJonathan Corbet  acpi=ht
179*ff61f079SJonathan Corbet    Use ACPI boot table parsing, but don't enable ACPI interpreter
180*ff61f079SJonathan Corbet  acpi=force
181*ff61f079SJonathan Corbet    Force ACPI on (currently not needed)
182*ff61f079SJonathan Corbet  acpi=strict
183*ff61f079SJonathan Corbet    Disable out of spec ACPI workarounds.
184*ff61f079SJonathan Corbet  acpi_sci={edge,level,high,low}
185*ff61f079SJonathan Corbet    Set up ACPI SCI interrupt.
186*ff61f079SJonathan Corbet  acpi=noirq
187*ff61f079SJonathan Corbet    Don't route interrupts
188*ff61f079SJonathan Corbet  acpi=nocmcff
189*ff61f079SJonathan Corbet    Disable firmware first mode for corrected errors. This
190*ff61f079SJonathan Corbet    disables parsing the HEST CMC error source to check if
191*ff61f079SJonathan Corbet    firmware has set the FF flag. This may result in
192*ff61f079SJonathan Corbet    duplicate corrected error reports.
193*ff61f079SJonathan Corbet
194*ff61f079SJonathan CorbetPCI
195*ff61f079SJonathan Corbet===
196*ff61f079SJonathan Corbet
197*ff61f079SJonathan Corbet  pci=off
198*ff61f079SJonathan Corbet    Don't use PCI
199*ff61f079SJonathan Corbet  pci=conf1
200*ff61f079SJonathan Corbet    Use conf1 access.
201*ff61f079SJonathan Corbet  pci=conf2
202*ff61f079SJonathan Corbet    Use conf2 access.
203*ff61f079SJonathan Corbet  pci=rom
204*ff61f079SJonathan Corbet    Assign ROMs.
205*ff61f079SJonathan Corbet  pci=assign-busses
206*ff61f079SJonathan Corbet    Assign busses
207*ff61f079SJonathan Corbet  pci=irqmask=MASK
208*ff61f079SJonathan Corbet    Set PCI interrupt mask to MASK
209*ff61f079SJonathan Corbet  pci=lastbus=NUMBER
210*ff61f079SJonathan Corbet    Scan up to NUMBER busses, no matter what the mptable says.
211*ff61f079SJonathan Corbet  pci=noacpi
212*ff61f079SJonathan Corbet    Don't use ACPI to set up PCI interrupt routing.
213*ff61f079SJonathan Corbet
214*ff61f079SJonathan CorbetIOMMU (input/output memory management unit)
215*ff61f079SJonathan Corbet===========================================
216*ff61f079SJonathan CorbetMultiple x86-64 PCI-DMA mapping implementations exist, for example:
217*ff61f079SJonathan Corbet
218*ff61f079SJonathan Corbet   1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all
219*ff61f079SJonathan Corbet      (e.g. because you have < 3 GB memory).
220*ff61f079SJonathan Corbet      Kernel boot message: "PCI-DMA: Disabling IOMMU"
221*ff61f079SJonathan Corbet
222*ff61f079SJonathan Corbet   2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
223*ff61f079SJonathan Corbet      Kernel boot message: "PCI-DMA: using GART IOMMU"
224*ff61f079SJonathan Corbet
225*ff61f079SJonathan Corbet   3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
226*ff61f079SJonathan Corbet      e.g. if there is no hardware IOMMU in the system and it is need because
227*ff61f079SJonathan Corbet      you have >3GB memory or told the kernel to us it (iommu=soft))
228*ff61f079SJonathan Corbet      Kernel boot message: "PCI-DMA: Using software bounce buffering
229*ff61f079SJonathan Corbet      for IO (SWIOTLB)"
230*ff61f079SJonathan Corbet
231*ff61f079SJonathan Corbet::
232*ff61f079SJonathan Corbet
233*ff61f079SJonathan Corbet  iommu=[<size>][,noagp][,off][,force][,noforce]
234*ff61f079SJonathan Corbet  [,memaper[=<order>]][,merge][,fullflush][,nomerge]
235*ff61f079SJonathan Corbet  [,noaperture]
236*ff61f079SJonathan Corbet
237*ff61f079SJonathan CorbetGeneral iommu options:
238*ff61f079SJonathan Corbet
239*ff61f079SJonathan Corbet    off
240*ff61f079SJonathan Corbet      Don't initialize and use any kind of IOMMU.
241*ff61f079SJonathan Corbet    noforce
242*ff61f079SJonathan Corbet      Don't force hardware IOMMU usage when it is not needed. (default).
243*ff61f079SJonathan Corbet    force
244*ff61f079SJonathan Corbet      Force the use of the hardware IOMMU even when it is
245*ff61f079SJonathan Corbet      not actually needed (e.g. because < 3 GB memory).
246*ff61f079SJonathan Corbet    soft
247*ff61f079SJonathan Corbet      Use software bounce buffering (SWIOTLB) (default for
248*ff61f079SJonathan Corbet      Intel machines). This can be used to prevent the usage
249*ff61f079SJonathan Corbet      of an available hardware IOMMU.
250*ff61f079SJonathan Corbet
251*ff61f079SJonathan Corbetiommu options only relevant to the AMD GART hardware IOMMU:
252*ff61f079SJonathan Corbet
253*ff61f079SJonathan Corbet    <size>
254*ff61f079SJonathan Corbet      Set the size of the remapping area in bytes.
255*ff61f079SJonathan Corbet    allowed
256*ff61f079SJonathan Corbet      Overwrite iommu off workarounds for specific chipsets.
257*ff61f079SJonathan Corbet    fullflush
258*ff61f079SJonathan Corbet      Flush IOMMU on each allocation (default).
259*ff61f079SJonathan Corbet    nofullflush
260*ff61f079SJonathan Corbet      Don't use IOMMU fullflush.
261*ff61f079SJonathan Corbet    memaper[=<order>]
262*ff61f079SJonathan Corbet      Allocate an own aperture over RAM with size 32MB<<order.
263*ff61f079SJonathan Corbet      (default: order=1, i.e. 64MB)
264*ff61f079SJonathan Corbet    merge
265*ff61f079SJonathan Corbet      Do scatter-gather (SG) merging. Implies "force" (experimental).
266*ff61f079SJonathan Corbet    nomerge
267*ff61f079SJonathan Corbet      Don't do scatter-gather (SG) merging.
268*ff61f079SJonathan Corbet    noaperture
269*ff61f079SJonathan Corbet      Ask the IOMMU not to touch the aperture for AGP.
270*ff61f079SJonathan Corbet    noagp
271*ff61f079SJonathan Corbet      Don't initialize the AGP driver and use full aperture.
272*ff61f079SJonathan Corbet    panic
273*ff61f079SJonathan Corbet      Always panic when IOMMU overflows.
274*ff61f079SJonathan Corbet
275*ff61f079SJonathan Corbetiommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
276*ff61f079SJonathan Corbetimplementation:
277*ff61f079SJonathan Corbet
278*ff61f079SJonathan Corbet    swiotlb=<slots>[,force,noforce]
279*ff61f079SJonathan Corbet      <slots>
280*ff61f079SJonathan Corbet        Prereserve that many 2K slots for the software IO bounce buffering.
281*ff61f079SJonathan Corbet      force
282*ff61f079SJonathan Corbet        Force all IO through the software TLB.
283*ff61f079SJonathan Corbet      noforce
284*ff61f079SJonathan Corbet        Do not initialize the software TLB.
285*ff61f079SJonathan Corbet
286*ff61f079SJonathan Corbet
287*ff61f079SJonathan CorbetMiscellaneous
288*ff61f079SJonathan Corbet=============
289*ff61f079SJonathan Corbet
290*ff61f079SJonathan Corbet  nogbpages
291*ff61f079SJonathan Corbet    Do not use GB pages for kernel direct mappings.
292*ff61f079SJonathan Corbet  gbpages
293*ff61f079SJonathan Corbet    Use GB pages for kernel direct mappings.
294*ff61f079SJonathan Corbet
295*ff61f079SJonathan Corbet
296*ff61f079SJonathan CorbetAMD SEV (Secure Encrypted Virtualization)
297*ff61f079SJonathan Corbet=========================================
298*ff61f079SJonathan CorbetOptions relating to AMD SEV, specified via the following format:
299*ff61f079SJonathan Corbet
300*ff61f079SJonathan Corbet::
301*ff61f079SJonathan Corbet
302*ff61f079SJonathan Corbet   sev=option1[,option2]
303*ff61f079SJonathan Corbet
304*ff61f079SJonathan CorbetThe available options are:
305*ff61f079SJonathan Corbet
306*ff61f079SJonathan Corbet   debug
307*ff61f079SJonathan Corbet     Enable debug messages.
308