Lines Matching +full:pci +full:- +full:iommu

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* pci_impl.h: Helper definitions for PCI controller support.
12 #include <linux/pci.h>
16 #include <asm/iommu.h>
18 /* The abstraction used here is that there are PCI controllers,
19  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20  * underneath.  Each PCI bus module uses an IOMMU (shared by both
21  * PBMs of a controller, or per-PBM), and if a streaming buffer
22  * is present, each PCI bus module has its own. (ie. the IOMMU
24  * Furthermore, each PCI bus module controls its own autonomous
25  * PCI bus.
29 	(*((STC)->strbuf_flushflag) = 0UL)
31 	(*((STC)->strbuf_flushflag) != 0UL)
74 	/* Opaque 32-bit system bus Port ID. */
77 	/* Opaque 32-bit handle used for hypervisor calls.  */
90 	/* Name used for top-level resources. */
107 	/* Base of PCI Config space, can be per-PBM or shared. */
110 	/* This will be 12 on PCI-E controllers, 8 elsewhere.  */
149 	/* IOMMU state, potentially shared by both PBM segments. */
150 	struct iommu			*iommu;  member
152 	/* Now things for the actual PCI bus probes. */
165 /* PCI bus scanning and fixup support. */