| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
16 distinct functions, reference each of them under its own property, giving it a
18 several GPIOs serve the same function (e.g. a parallel data line).
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
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| H A D | nvidia,tegra186-gpio.txt | 1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
15 register set. These registers exist in a single contiguous block of physical
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
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| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
20 The Tegra186 GPIO controller allows software to set the IO direction of,
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
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| H A D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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| H A D | snps,dw-apb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-ap
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| H A D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio
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| H A D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
4 registers with each set controlling a bank of up to 32 pins. A single
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
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| H A D | mrvl-gpio.txt | 1 * Marvell PXA GPIO controller
4 - compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
5 "intel,pxa27x-gpio", "intel,pxa3xx-gpio",
6 "marvell,pxa93x-gpio", "marvell,mmp-gpio",
7 "marvell,mmp2-gpio" or marvell,pxa1928-gpio.
8 - reg : Address and length of the register set for the device
9 - interrupts : Should be the port interrupt shared by all gpio pins.
10 There're three gpio interrupts in arch-pxa, and they're gpio0,
11 gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
13 - interrupt-names : Should be the names of irq resources. Each interrupt
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| /freebsd/sys/dts/ |
| H A D | bindings-gpio.txt | 2 GPIO configuration.
5 1. Properties for GPIO Controllers
7 1.1 #gpio-cells
9 Property: #gpio-cells
13 Description: The #gpio-cells property defines the number of cells required
14 to encode a gpio specifier.
17 1.2 gpio-controller
19 Property: gpio-controller
23 Description: The presence of a gpio-controller property defines a node as a
24 GPIO controller node.
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | qcom,pmic-gpio.txt | 1 Qualcomm PMIC GPIO block
3 This binding describes the GPIO block(s) found in the 8xxx series of
6 - compatible:
10 "qcom,pm8005-gpio"
11 "qcom,pm8018-gpio"
12 "qcom,pm8038-gpio"
13 "qcom,pm8058-gpio"
14 "qcom,pm8916-gpio"
15 "qcom,pm8917-gpio"
16 "qcom,pm8921-gpio"
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| H A D | ingenic,pinctrl.txt | 3 Please refer to pinctrl-bindings.txt in this directory for details of the
7 For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
9 GPIO port configuration registers and it is typical to refer to pins using the
10 naming scheme "PxN" where x is a character identifying the GPIO port with
12 pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
13 PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
14 contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
15 jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
19 --------------------
21 - compatible: One of:
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| H A D | brcm,bcm2835-gpio.txt | 1 Broadcom BCM2835 GPIO (and pinmux) controller
3 The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
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| H A D | ingenic,pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
18 a single pincontroller.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
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| H A D | renesas,rza1-pinctrl.txt | 1 Renesas RZ/A1 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
7 Each "port" features up to 16 pins, each of them configurable for GPIO
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
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| H A D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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| H A D | renesas,pfc-pinctrl.txt | 1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
4 R8A73A4 and R8A7740 it also acts as a GPIO controller.
8 -----------
12 - compatible: should be one of the following.
13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
17 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | cirrus,cs35l45.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
14 CS35L45 is a Boosted Mono Class D Amplifier with DSP
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
28 '#sound-dai-cells':
31 reset-gpios:
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| /freebsd/sys/dev/sdhci/ |
| H A D | sdhci_fdt_gpio.c | 1 /*-
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * Support routines usable by any SoC sdhci bridge driver that uses gpio pins
33 #include <sys/gpio.h>
38 #include <dev/gpio/gpiobusvar.h>
65 struct sdhci_fdt_gpio *gpio = arg; in cd_intr() local
67 sdhci_handle_card_present(gpio->slot, sdhci_fdt_gpio_get_present(gpio)); in cd_intr()
74 cd_setup(struct sdhci_fdt_gpio *gpio, phandle_t node) in cd_setup() argument
80 dev = gpio->dev; in cd_setup()
83 * If the device is flagged as non-removable, set that slot option, and in cd_setup()
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | gpio-poweroff.txt | 1 Driver a GPIO line that can be used to turn the power off.
4 At driver load time, the driver will request the given gpio line and
5 install a handler to power off the system. If the optional properties
6 'input' is not found, the GPIO line will be driven in the inactive
9 When the power-off handler is called, the gpio is configured as an
10 output, and drive active, so triggering a level triggered power off
11 condition. This will also cause an inactive->active edge condition, so
12 triggering positive edge triggered power off. After a delay of 100ms,
13 the GPIO is set to inactive, thus causing an active->inactive edge,
15 delay the GPIO is driver active again. If the power is still on and
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| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio
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| H A D | gpio-restart.txt | 1 Drive a GPIO line that can be used to restart the system from a restart
5 time, the driver will request the given gpio line and install a restart
6 handler. If the optional properties 'open-source' is not found, the GPIO line
11 priority order. The gpio is configured as an output, and driven active,
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
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| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
5 Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
7 On CPM2 devices, all ports are 32bit ports and use a common register layout.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | kontron,sl28cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
14 watchdog, fan monitoring, PWM controller, interrupt controller and a
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
38 interrupt-controller: true
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/sound/ |
| H A D | cs35l45.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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