1*c66ec88fSEmmanuel VadotEvery GPIO controller node must have #gpio-cells property defined, 2*c66ec88fSEmmanuel Vadotthis information will be used to translate gpio-specifiers. 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotOn CPM1 devices, all ports are using slightly different register layouts. 5*c66ec88fSEmmanuel VadotPorts A, C and D are 16bit ports and Ports B and E are 32bit ports. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotOn CPM2 devices, all ports are 32bit ports and use a common register layout. 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel VadotRequired properties: 10*c66ec88fSEmmanuel Vadot- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", 11*c66ec88fSEmmanuel Vadot "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", 12*c66ec88fSEmmanuel Vadot "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" 13*c66ec88fSEmmanuel Vadot- #gpio-cells : Should be two. The first cell is the pin number and the 14*c66ec88fSEmmanuel Vadot second cell is used to specify optional parameters (currently unused). 15*c66ec88fSEmmanuel Vadot- gpio-controller : Marks the port as GPIO controller. 16*c66ec88fSEmmanuel VadotOptional properties: 17*c66ec88fSEmmanuel Vadot- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C 18*c66ec88fSEmmanuel Vadot on CPM1), this item tells which ports have an associated interrupt (ports are 19*c66ec88fSEmmanuel Vadot listed in the same order as in PCINT register) 20*c66ec88fSEmmanuel Vadot- interrupts : This property provides the list of interrupt for each GPIO having 21*c66ec88fSEmmanuel Vadot one as described by the fsl,cpm1-gpio-irq-mask property. There should be as 22*c66ec88fSEmmanuel Vadot many interrupts as number of ones in the mask property. The first interrupt in 23*c66ec88fSEmmanuel Vadot the list corresponds to the most significant bit of the mask. 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel VadotExample of four SOC GPIO banks defined as gpio-controller nodes: 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel Vadot CPM1_PIO_A: gpio-controller@950 { 28*c66ec88fSEmmanuel Vadot #gpio-cells = <2>; 29*c66ec88fSEmmanuel Vadot compatible = "fsl,cpm1-pario-bank-a"; 30*c66ec88fSEmmanuel Vadot reg = <0x950 0x10>; 31*c66ec88fSEmmanuel Vadot gpio-controller; 32*c66ec88fSEmmanuel Vadot }; 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel Vadot CPM1_PIO_B: gpio-controller@ab8 { 35*c66ec88fSEmmanuel Vadot #gpio-cells = <2>; 36*c66ec88fSEmmanuel Vadot compatible = "fsl,cpm1-pario-bank-b"; 37*c66ec88fSEmmanuel Vadot reg = <0xab8 0x10>; 38*c66ec88fSEmmanuel Vadot gpio-controller; 39*c66ec88fSEmmanuel Vadot }; 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel Vadot CPM1_PIO_C: gpio-controller@960 { 42*c66ec88fSEmmanuel Vadot #gpio-cells = <2>; 43*c66ec88fSEmmanuel Vadot compatible = "fsl,cpm1-pario-bank-c"; 44*c66ec88fSEmmanuel Vadot reg = <0x960 0x10>; 45*c66ec88fSEmmanuel Vadot fsl,cpm1-gpio-irq-mask = <0x0fff>; 46*c66ec88fSEmmanuel Vadot interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; 47*c66ec88fSEmmanuel Vadot interrupt-parent = <&CPM_PIC>; 48*c66ec88fSEmmanuel Vadot gpio-controller; 49*c66ec88fSEmmanuel Vadot }; 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel Vadot CPM1_PIO_E: gpio-controller@ac8 { 52*c66ec88fSEmmanuel Vadot #gpio-cells = <2>; 53*c66ec88fSEmmanuel Vadot compatible = "fsl,cpm1-pario-bank-e"; 54*c66ec88fSEmmanuel Vadot reg = <0xac8 0x18>; 55*c66ec88fSEmmanuel Vadot gpio-controller; 56*c66ec88fSEmmanuel Vadot }; 57