Lines Matching +full:a +full:- +full:gpio

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10   - Linus Walleij <linus.walleij@linaro.org>
11   - Bartosz Golaszewski <brgl@bgdev.pl>
14   Some simple GPIO controllers may consist of a single data register or a pair
15   of set/clear-bit registers. Such controllers are common for glue logic in
16   FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17   NAND-style parallel busses.
22       - brcm,bcm6345-gpio
23       - ni,169445-nand-gpio
24       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
26   big-endian: true
28   '#gpio-cells':
31   gpio-controller: true
33   little-endian: true
38       A list of registers in the controller. The width of each register is
40       of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
42       - description:
43           Register to READ the value of the GPIO lines. If GPIO line is high,
44           the bit will be set. If the GPIO line is low, the bit will be cleared.
47       - description:
48           Register to SET the value of the GPIO lines. Setting a bit in this
49           register will drive the GPIO line high.
50       - description:
51           Register to CLEAR the value of the GPIO lines. Setting a bit in this
52           register will drive the GPIO line low. If this register is omitted,
53           the SET register will be used to clear the GPIO lines as well, by
55       - description:
56           Register to set the line as OUTPUT. Setting a bit in this register
57           will turn that line into an output line. Conversely, clearing a bit
59       - description:
60           Register to set this line as INPUT. Setting a bit in this register
61           will turn that line into an input line. Conversely, clearing a bit
64   reg-names:
69         - dat
70         - set
71         - clr
72         - dirout
73         - dirin
75   native-endian: true
77   no-output:
80       If this property is present, the controller cannot drive the GPIO lines.
83   - compatible
84   - reg
85   - reg-names
86   - '#gpio-cells'
87   - gpio-controller
92   - |
93     gpio@1f300010 {
94       compatible = "ni,169445-nand-gpio";
96       reg-names = "dat";
97       gpio-controller;
98       #gpio-cells = <2>;
101     gpio@e0100000 {
102       compatible = "wd,mbl-gpio";
103       reg-names = "dat";
105       #gpio-cells = <2>;
106       gpio-controller;
107       no-output;
110     gpio@fffe0406 {
111       compatible = "brcm,bcm6345-gpio";
112       reg-names = "dirout", "dat";
114       native-endian;
115       gpio-controller;
116       #gpio-cells = <2>;