Lines Matching +full:a +full:- +full:gpio
1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
15 register set. These registers exist in a single contiguous block of physical
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
30 Tegra HW documentation describes a unified naming convention for all GPIOs
31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33 name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
45 sorted within a particular controller. Drivers need to map between the DT GPIO
46 IDs and HW register offsets using a lookup table.
48 Each GPIO controller can generate a number of interrupt signals. Each signal
49 represents the aggregate status for all GPIOs within a set of ports. Thus, the
50 number of interrupt signals generated by a controller varies as a rough function
52 both the overall controller HW module and the sets-of-ports as "controllers".
54 Each GPIO controller in fact generates multiple interrupts signals for each set
55 of ports. Each GPIO may be configured to feed into a specific one of the
56 interrupt signals generated by a set-of-ports. The intent is for each generated
57 signal to be routed to a different CPU, thus allowing different CPUs to each
58 handle subsets of the interrupts within a port. The status of each of these
59 per-port-set signals is reported via a separate register. Thus, a driver needs
63 define a property to configure this.
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - "nvidia,tegra194-gpio".
72 - "nvidia,tegra194-gpio-aon".
73 - reg-names
75 Contains a list of names for the register spaces described by the reg
77 - "gpio": Mandatory. GPIO control registers. This may cover either:
78 a) The single physical alias that this OS should use.
82 - "security": Optional. Security configuration registers.
84 using this reg-names property to do so.
85 - reg
87 Must contain one entry per entry in the reg-names property, in a matching
89 - interrupts
94 - "nvidia,tegra186-gpio": 6 entries.
95 - "nvidia,tegra186-gpio-aon": 1 entry.
96 - "nvidia,tegra194-gpio": 6 entries.
97 - "nvidia,tegra194-gpio-aon": 1 entry.
98 - gpio-controller
100 Marks the device node as a GPIO controller/provider.
101 - #gpio-cells
102 Single-cell integer.
104 Indicates how many cells are used in a consumer's GPIO specifier.
106 - The first cell is the pin number.
107 See <dt-bindings/gpio/tegra186-gpio.h>.
108 - The second cell contains flags:
109 - Bit 0 specifies polarity
110 - 0: Active-high (normal).
111 - 1: Active-low (inverted).
112 - interrupt-controller
115 - #interrupt-cells
116 Single-cell integer.
118 Indicates how many cells are used in a consumer's interrupt specifier.
120 - The first cell is the GPIO number.
121 See <dt-bindings/gpio/tegra186-gpio.h>.
122 - The second cell is contains flags:
123 - Bits [3:0] indicate trigger type and level:
124 - 1: Low-to-high edge triggered.
125 - 2: High-to-low edge triggered.
126 - 4: Active high level-sensitive.
127 - 8: Active low level-sensitive.
132 #include <dt-bindings/interrupt-controller/irq.h>
134 gpio@2200000 {
135 compatible = "nvidia,tegra186-gpio";
136 reg-names = "security", "gpio";
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
153 gpio@c2f0000 {
154 compatible = "nvidia,tegra186-gpio-aon";
155 reg-names = "security", "gpio";
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <2>;