Lines Matching +full:a +full:- +full:gpio

1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
4 registers with each set controlling a bank of up to 32 pins.  A single
9 - compatible:
10     Must be "brcm,brcmstb-gpio"
12 - reg:
14     the brcmstb GPIO controller registers
16 - #gpio-cells:
19     bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
22     Specifies that the node is a GPIO controller.
24 - brcm,gpio-bank-widths:
25     Number of GPIO lines for each bank.  Number of elements must
30 - interrupts:
31     The interrupt shared by all GPIO lines for this controller.
33 - interrupts-extended:
36     'interrupt-parent'.  Wakeup-capable GPIO controllers often route their
37     wakeup interrupt lines through a different interrupt controller than the
40 - #interrupt-cells:
41     Should be <2>.  The first cell is the GPIO number, the second should specify
43     - bits[3:0] trigger type and level flags
44         1 = low-to-high edge triggered
45         2 = high-to-low edge triggered
46         4 = active high level-sensitive
47         8 = active low level-sensitive
49     See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
51 - interrupt-controller:
54 - wakeup-source:
55     GPIOs for this controller can be used as a wakeup source
58 	upg_gio: gpio@f040a700 {
59 		#gpio-cells = <2>;
60 		#interrupt-cells = <2>;
61 		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
62 		gpio-controller;
63 		interrupt-controller;
65 		interrupt-parent = <&irq0_intc>;
67 		brcm,gpio-bank-widths = <32 32 32 24>;
70 	upg_gio_aon: gpio@f04172c0 {
71 		#gpio-cells = <2>;
72 		#interrupt-cells = <2>;
73 		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
74 		gpio-controller;
75 		interrupt-controller;
77 		interrupt-parent = <&irq0_aon_intc>;
79 		interrupts-extended = <&irq0_aon_intc 0x6>,
81 		wakeup-source;
82 		brcm,gpio-bank-widths = <18 4>;