Lines Matching +full:a +full:- +full:gpio
1 Renesas RZ/A1 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
7 Each "port" features up to 16 pins, each of them configurable for GPIO
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
20 - reg
27 pinctrl: pin-controller@fcfe3000 {
28 compatible = "renesas,r7s72100-ports";
33 Sub-nodes
34 ---------
36 The child nodes of the pin controller node describe a pin multiplexing
37 function or a GPIO controller alternatively.
39 - Pin multiplexing sub-nodes:
40 A pin multiplexing sub-node describes how to configure a set of
41 (or a single) pin in some desired alternate function mode.
42 A single sub-node may define several pin configurations.
43 A few alternate function require special pin configuration flags to be
45 The hardware reference manual specifies when a pin function requires
50 Please refer to pinctrl-bindings.txt to get to know more on generic
53 The allowed generic formats for a pin multiplexing sub-node are the
56 node-1 {
61 node-2 {
62 sub-node-1 {
67 sub-node-2 {
74 sub-node-n {
83 Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
88 client-1 {
90 pinctrl-0 = <&node-1>;
94 client-2 {
96 pinctrl-0 = <&node-2>;
101 - pinmux:
103 When a pin has to be configured in alternate function mode, use this
108 argument list of a single "pinmux" property.
112 <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
117 - input-enable:
120 - output-high:
122 operations. output-low can be used alternatively, as line value is
125 The hardware reference manual specifies when a pin has to be configured to
126 work in bi-directional mode and when the IO direction has to be specified
127 by software. Bi-directional pins are managed by the pin controller driver
132 A serial communication interface with a TX output pin and an RX input pin.
144 I2c master: both SDA and SCL pins need bi-directional operations
154 Both need to work in bi-directional mode, the driver manages this internally.
157 Multi-function timer input and output compare pins.
165 input-enable;
170 output-enable;
177 pinctrl-0 = <&tioc0_pins>;
186 - GPIO controller sub-nodes:
187 Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
189 generally speaking, each of them can be configured in GPIO ("port") mode
191 Describe GPIO controllers using sub-nodes with the following properties.
194 - gpio-controller
195 empty property as defined by the GPIO bindings documentation.
196 - #gpio-cells
197 number of cells required to identify and configure a GPIO.
199 - gpio-ranges
200 Describes a GPIO controller specifying its specific pin base, the pin
202 pins, as defined by the GPIO bindings documentation. Refer to
203 Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
207 A GPIO controller node, controlling 16 pins indexed from 0.
208 The GPIO controller base in the global pin indexing space is pin 48, thus
209 pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
212 port3: gpio-3 {
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pinctrl 0 48 16>;
218 A device node willing to use pins controlled by this GPIO controller, shall