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/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
41 st-spics,sw-enable-bit:
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/linux/drivers/usb/typec/mux/
H A Dfsa4480.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Linaro Ltd.
4 * Copyright (C) 2018-2020 The Linux Foundation
37 #define FSA4480_ENABLE_DEVICE BIT(7)
40 #define FSA4480_ENABLE_SENSE BIT(2)
41 #define FSA4480_ENABLE_MIC BIT(1)
42 #define FSA4480_ENABLE_AGND BIT(0)
46 #define FSA4480_SEL_SENSE BIT(2)
47 #define FSA4480_SEL_MIC BIT(1)
48 #define FSA4480_SEL_AGND BIT(0)
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H A Dwcd939x-usbss.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define WCD_USBSS_DP_DN_MISC1_DP_PCOMP_2X_DYN_BST_ON_EN BIT(3)
23 #define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_ON_EN BIT(0)
27 #define WCD_USBSS_MG1_EN_CT_SNS_EN BIT(1)
31 #define WCD_USBSS_MG1_BIAS_PCOMP_DYN_BST_EN BIT(3)
35 #define WCD_USBSS_MG1_MISC_PCOMP_2X_DYN_BST_ON_EN BIT(5)
39 #define WCD_USBSS_MG2_EN_CT_SNS_EN BIT(1)
43 #define WCD_USBSS_MG2_BIAS_PCOMP_DYN_BST_EN BIT(3)
47 #define WCD_USBSS_MG2_MISC_PCOMP_2X_DYN_BST_ON_EN BIT(5)
61 #define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DEVICE_ENABLE BIT(7)
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H A Dit5205.c1 // SPDX-License-Identifier: GPL-2.0
3 * ITE IT5205 Type-C USB alternate mode passive mux
25 #define IT5205FN_CHIP_ID 0x35303235 /* "5025" -> "5205" */
29 #define IT5205_MUX_POWER_DOWN BIT(0)
33 #define IT5205_POLARITY_INVERTED BIT(4)
55 #define IT5205_CSBUSR_SWITCH BIT(0)
59 #define IT5205_ISR_CSBU_MASK BIT(4)
60 #define IT5205_ISR_CSBU_OVP BIT(0)
65 struct typec_switch_dev *sw; member
69 static int it5205_switch_set(struct typec_switch_dev *sw, enum typec_orientation orientation) in it5205_switch_set() argument
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H A Dnb7vpq904m.c1 // SPDX-License-Identifier: GPL-2.0+
3 * OnSemi NB7VPQ904M Type-C driver
14 #include <drm/bridge/aux-bridge.h>
29 #define GEN_DEV_SET_CHIP_EN BIT(0)
30 #define GEN_DEV_SET_CHNA_EN BIT(4)
31 #define GEN_DEV_SET_CHNB_EN BIT(5)
32 #define GEN_DEV_SET_CHNC_EN BIT(6)
33 #define GEN_DEV_SET_CHND_EN BIT(7)
67 struct typec_switch_dev *sw; member
74 struct mutex lock; /* protect non-concurrent retimer & switch */
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/linux/arch/alpha/include/uapi/asm/
H A Dfpu.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 * Alpha floating-point control register defines:
23 #define FPCR_SUM (1UL<<63) /* summary bit */
25 #define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */
27 #define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */
35 * IEEE trap enables are implemented in software. These per-thread
38 * floating-point enable bit (which is architected). On top of that,
83 * Convert the software IEEE trap enable and status bits into the
88 * receive my thanks for making all the not-implemented fpcr bits
93 ieee_swcr_to_fpcr(unsigned long sw) in ieee_swcr_to_fpcr() argument
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 /* Top-level registers */
14 * 1=Assert SW reset of timing feature. 0=Release reset.
16 * 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset.
18 * 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset.
20 * 1=Assert SW reset on IP core. 0=Release reset.
24 #define MIPI_DSI_TOP_SW_RESET_DWC BIT(0)
25 #define MIPI_DSI_TOP_SW_RESET_INTR BIT(1)
26 #define MIPI_DSI_TOP_SW_RESET_DPI BIT(2)
27 #define MIPI_DSI_TOP_SW_RESET_TIMING BIT(3)
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/linux/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
48 * SW Free Queue, HW Free Queue,
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
182 unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
187 /* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
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/linux/drivers/thunderbolt/
H A Dtmu.c1 // SPDX-License-Identifier: GPL-2.0
46 return "uni-directional, LowRes"; in tmu_mode_name()
48 return "uni-directional, HiFi"; in tmu_mode_name()
50 return "bi-directional, HiFi"; in tmu_mode_name()
52 return "enhanced uni-directional, MedRes"; in tmu_mode_name()
58 static bool tb_switch_tmu_enhanced_is_supported(const struct tb_switch *sw) in tb_switch_tmu_enhanced_is_supported() argument
60 return usb4_switch_version(sw) > 1; in tb_switch_tmu_enhanced_is_supported()
63 static int tb_switch_set_tmu_mode_params(struct tb_switch *sw, in tb_switch_set_tmu_mode_params() argument
72 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, in tb_switch_set_tmu_mode_params()
73 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
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H A Dtb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - bus logic (NHI independent)
13 #include <linux/nvmem-provider.h>
24 #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0)
26 #define QUIRK_NO_CLX BIT(1)
28 #define QUIRK_KEEP_POWER_IN_DP_REDRIVE BIT(2)
31 * struct tb_nvm - Structure holding NVM information
38 * @non_active: Non-active portion NVMem device
79 * enum tb_switch_tmu_mode - TMU mode
81 * @TB_SWITCH_TMU_MODE_LOWRES: Uni-directional, normal mode
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H A Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
37 static struct nvm_auth_status *__nvm_get_auth_status(const struct tb_switch *sw) in __nvm_get_auth_status() argument
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
49 static void nvm_get_auth_status(const struct tb_switch *sw, u32 *status) in nvm_get_auth_status() argument
54 st = __nvm_get_auth_status(sw); in nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
60 static void nvm_set_auth_status(const struct tb_switch *sw, u32 status) in nvm_set_auth_status() argument
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
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H A Dcap.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - capabilities lookup
16 #define TMU_ACCESS_EN BIT(20)
18 static int tb_port_enable_tmu(struct tb_port *port, bool enable) in tb_port_enable_tmu() argument
20 struct tb_switch *sw = port->sw; in tb_port_enable_tmu() local
28 if (tb_switch_is_light_ridge(sw)) in tb_port_enable_tmu()
30 else if (tb_switch_is_eagle_ridge(sw)) in tb_port_enable_tmu()
35 ret = tb_sw_read(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu()
39 if (enable) in tb_port_enable_tmu()
44 return tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu()
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H A Dusb4.c1 // SPDX-License-Identifier: GPL-2.0
53 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode, in usb4_native_switch_op() argument
62 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); in usb4_native_switch_op()
67 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9, in usb4_native_switch_op()
74 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); in usb4_native_switch_op()
78 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); in usb4_native_switch_op()
82 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); in usb4_native_switch_op()
87 return -EOPNOTSUPP; in usb4_native_switch_op()
94 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); in usb4_native_switch_op()
99 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9, in usb4_native_switch_op()
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H A Dlc.c1 // SPDX-License-Identifier: GPL-2.0
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
15 * @sw: Switch whose UUID is read
18 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) in tb_lc_read_uuid() argument
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 static int read_lc_desc(struct tb_switch *sw, u32 *desc) in read_lc_desc() argument
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
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/linux/drivers/extcon/
H A Dextcon-intel-cht-wc.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
10 #include <linux/extcon-provider.h>
24 #include "extcon-intel.h"
29 #define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
30 #define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
31 #define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
32 #define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
33 #define CHT_WC_CHGRCTRL0_TTLCK BIT(4)
34 #define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5)
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/linux/drivers/clk/bcm/
H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
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/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_hw.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2019-2020 Marvell International Ltd. All rights reserved. */
17 PRESTERA_FDB_FLUSH_MODE_DYNAMIC = BIT(0),
18 PRESTERA_FDB_FLUSH_MODE_STATIC = BIT(1),
140 (struct prestera_switch *sw, struct prestera_event *evt, void *arg);
152 int prestera_hw_switch_init(struct prestera_switch *sw);
153 void prestera_hw_switch_fini(struct prestera_switch *sw);
154 int prestera_hw_switch_ageing_set(struct prestera_switch *sw, u32 ageing_ms);
155 int prestera_hw_switch_mac_set(struct prestera_switch *sw, const char *mac);
184 int prestera_hw_port_learning_set(struct prestera_port *port, bool enable);
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
179 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
182 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
185 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
235 …USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change t…
236 …USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the …
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/linux/arch/sparc/include/asm/
H A Dtsunami.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * -----------------------------------------------------------------------
16 * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
17 * -----------------------------------------------------------------------
18 * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
20 * SW: Enable Software Table Walks 0=off 1=on
21 * AV: Address View bit
22 * DV: Data View bit
23 * MV: Memory View bit
27 * PE: Parity Enable 0=off 1=on
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
76 * descriptors before SW gets an interrupt and overwrites SW head, the gen bit
78 * be gone forever and SW has no reasonable way to tell that this has happened.
79 * From SW perspective, when we finally get an interrupt, it looks like we're
84 #define IDPF_RX_BUFQ_WORKING_SET(rxq) ((rxq)->desc_count - 1)
88 if (unlikely(++(ntc) == (rxq)->desc_count)) { \
96 if (unlikely(++(idx) == (q)->desc_count)) \
106 /* Minimum number of descriptors between 2 descriptors with the RE bit set;
111 #define IDPF_RFL_BI_GEN_M BIT(16)
118 ((((txq)->next_to_clean > (txq)->next_to_use) ? 0 : (txq)->desc_count) + \
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
172 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
175 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
178 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
227 …USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change …
228 …USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the …
244 …USHORT ASIC_Init; //Function Table, used by various SW components,lat…
246 …USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW comp…
249 …USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW comp…
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/linux/arch/mips/kernel/
H A Dsmp-bmips.c40 #include <asm/cpu-features.h>
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
68 /* SW interrupts 0,1 are used for interprocessor signaling */
95 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other in bmips_smp_setup()
113 /* enable raceless SW interrupts */ in bmips_smp_setup()
122 /* clear any pending SW interrupts */ in bmips_smp_setup()
162 * IPI IRQ setup - runs on CPU0
189 * Tell the hardware to boot CPUx - runs on CPU0
199 * bmips_reset_nmi_vec @ a000_0000 -> in bmips_boot_secondary()
200 * bmips_smp_entry -> in bmips_boot_secondary()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8mq-usb.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define PHY_CTRL0_REF_SSP_EN BIT(2)
21 #define PHY_CTRL1_RESET BIT(0)
22 #define PHY_CTRL1_COMMONONN BIT(1)
23 #define PHY_CTRL1_ATERESET BIT(3)
24 #define PHY_CTRL1_VDATSRCENB0 BIT(19)
25 #define PHY_CTRL1_VDATDETENB0 BIT(20)
28 #define PHY_CTRL2_TXENABLEN0 BIT(8)
29 #define PHY_CTRL2_OTG_DISABLE BIT(9)
42 #define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23)
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/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /*! This is used to store the 48 bit value used to compare SA, DA or
17 /*! This is used to store the 16 bit ethertype value used for
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
22 * will match successfully. The total data is 64 bit, i.e. 16 nibbles
52 /*! The 8 bit value used to compare with extracted value for byte 3. */
54 /*! The 8 bit value used to compare with extracted value for byte 2. */
56 /*! The 8 bit value used to compare with extracted value for byte 1. */
58 /*! The 8 bit value used to compare with extracted value for byte 0. */
60 /*! The 8 bit TCI field used to compare with extracted value. */
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/linux/drivers/block/
H A Dswim3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/blk-mq.h>
182 int cur_cyl; /* cylinder head is on, or -1 */
193 int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
209 #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
210 #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
211 #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
214 #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
258 struct request *req = fs->cur_req; in swim3_end_request()
268 fs->cur_req = NULL; in swim3_end_request()
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