Lines Matching +full:sw +full:- +full:enable +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7  * Alpha floating-point control register defines:
23 #define FPCR_SUM	(1UL<<63)	/* summary bit */
25 #define FPCR_DYN_SHIFT	58		/* first dynamic rounding mode bit */
27 #define FPCR_DYN_MINUS	 (0x1UL << FPCR_DYN_SHIFT)	/* towards -INF */
35  * IEEE trap enables are implemented in software.  These per-thread
38  * floating-point enable bit (which is architected).  On top of that,
83  * Convert the software IEEE trap enable and status bits into the
88  * receive my thanks for making all the not-implemented fpcr bits
93 ieee_swcr_to_fpcr(unsigned long sw)  in ieee_swcr_to_fpcr()  argument
96 	fp = (sw & IEEE_STATUS_MASK) << 35;  in ieee_swcr_to_fpcr()
97 	fp |= (sw & IEEE_MAP_DMZ) << 36;  in ieee_swcr_to_fpcr()
98 	fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0);  in ieee_swcr_to_fpcr()
99 	fp |= (~sw & (IEEE_TRAP_ENABLE_INV  in ieee_swcr_to_fpcr()
102 	fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57;  in ieee_swcr_to_fpcr()
103 	fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);  in ieee_swcr_to_fpcr()
104 	fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41;  in ieee_swcr_to_fpcr()
111 	unsigned long sw;  in ieee_fpcr_to_swcr()  local
112 	sw = (fp >> 35) & IEEE_STATUS_MASK;  in ieee_fpcr_to_swcr()
113 	sw |= (fp >> 36) & IEEE_MAP_DMZ;  in ieee_fpcr_to_swcr()
114 	sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV  in ieee_fpcr_to_swcr()
117 	sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE);  in ieee_fpcr_to_swcr()
118 	sw |= (fp >> 47) & IEEE_MAP_UMZ;  in ieee_fpcr_to_swcr()
119 	sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO;  in ieee_fpcr_to_swcr()
120 	return sw;  in ieee_fpcr_to_swcr()