1*6f52b16cSGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 296433f6eSDavid Howells #ifndef _UAPI__ASM_ALPHA_FPU_H 396433f6eSDavid Howells #define _UAPI__ASM_ALPHA_FPU_H 496433f6eSDavid Howells 596433f6eSDavid Howells 696433f6eSDavid Howells /* 796433f6eSDavid Howells * Alpha floating-point control register defines: 896433f6eSDavid Howells */ 996433f6eSDavid Howells #define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */ 1096433f6eSDavid Howells #define FPCR_DNZ (1UL<<48) /* denorms to zero */ 1196433f6eSDavid Howells #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */ 1296433f6eSDavid Howells #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */ 1396433f6eSDavid Howells #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */ 1496433f6eSDavid Howells #define FPCR_INV (1UL<<52) /* invalid operation */ 1596433f6eSDavid Howells #define FPCR_DZE (1UL<<53) /* division by zero */ 1696433f6eSDavid Howells #define FPCR_OVF (1UL<<54) /* overflow */ 1796433f6eSDavid Howells #define FPCR_UNF (1UL<<55) /* underflow */ 1896433f6eSDavid Howells #define FPCR_INE (1UL<<56) /* inexact */ 1996433f6eSDavid Howells #define FPCR_IOV (1UL<<57) /* integer overflow */ 2096433f6eSDavid Howells #define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */ 2196433f6eSDavid Howells #define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */ 2296433f6eSDavid Howells #define FPCR_INED (1UL<<62) /* inexact disable (opt.) */ 2396433f6eSDavid Howells #define FPCR_SUM (1UL<<63) /* summary bit */ 2496433f6eSDavid Howells 2596433f6eSDavid Howells #define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */ 2696433f6eSDavid Howells #define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */ 2796433f6eSDavid Howells #define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */ 2896433f6eSDavid Howells #define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */ 2996433f6eSDavid Howells #define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */ 3096433f6eSDavid Howells #define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT) 3196433f6eSDavid Howells 3296433f6eSDavid Howells #define FPCR_MASK 0xffff800000000000L 3396433f6eSDavid Howells 3496433f6eSDavid Howells /* 3596433f6eSDavid Howells * IEEE trap enables are implemented in software. These per-thread 3696433f6eSDavid Howells * bits are stored in the "ieee_state" field of "struct thread_info". 3796433f6eSDavid Howells * Thus, the bits are defined so as not to conflict with the 3896433f6eSDavid Howells * floating-point enable bit (which is architected). On top of that, 3996433f6eSDavid Howells * we want to make these bits compatible with OSF/1 so 4096433f6eSDavid Howells * ieee_set_fp_control() etc. can be implemented easily and 4196433f6eSDavid Howells * compatibly. The corresponding definitions are in 4296433f6eSDavid Howells * /usr/include/machine/fpu.h under OSF/1. 4396433f6eSDavid Howells */ 4496433f6eSDavid Howells #define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */ 4596433f6eSDavid Howells #define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */ 4696433f6eSDavid Howells #define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */ 4796433f6eSDavid Howells #define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */ 4896433f6eSDavid Howells #define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */ 4996433f6eSDavid Howells #define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */ 5096433f6eSDavid Howells #define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\ 5196433f6eSDavid Howells IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\ 5296433f6eSDavid Howells IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO) 5396433f6eSDavid Howells 5496433f6eSDavid Howells /* Denorm and Underflow flushing */ 5596433f6eSDavid Howells #define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */ 5696433f6eSDavid Howells #define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */ 5796433f6eSDavid Howells 5896433f6eSDavid Howells #define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ) 5996433f6eSDavid Howells 6096433f6eSDavid Howells /* status bits coming from fpcr: */ 6196433f6eSDavid Howells #define IEEE_STATUS_INV (1UL<<17) 6296433f6eSDavid Howells #define IEEE_STATUS_DZE (1UL<<18) 6396433f6eSDavid Howells #define IEEE_STATUS_OVF (1UL<<19) 6496433f6eSDavid Howells #define IEEE_STATUS_UNF (1UL<<20) 6596433f6eSDavid Howells #define IEEE_STATUS_INE (1UL<<21) 6696433f6eSDavid Howells #define IEEE_STATUS_DNO (1UL<<22) 6796433f6eSDavid Howells 6896433f6eSDavid Howells #define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \ 6996433f6eSDavid Howells IEEE_STATUS_OVF | IEEE_STATUS_UNF | \ 7096433f6eSDavid Howells IEEE_STATUS_INE | IEEE_STATUS_DNO) 7196433f6eSDavid Howells 7296433f6eSDavid Howells #define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \ 7396433f6eSDavid Howells IEEE_STATUS_MASK | IEEE_MAP_MASK) 7496433f6eSDavid Howells 7596433f6eSDavid Howells #define IEEE_CURRENT_RM_SHIFT 32 7696433f6eSDavid Howells #define IEEE_CURRENT_RM_MASK (3UL<<IEEE_CURRENT_RM_SHIFT) 7796433f6eSDavid Howells 7896433f6eSDavid Howells #define IEEE_STATUS_TO_EXCSUM_SHIFT 16 7996433f6eSDavid Howells 8096433f6eSDavid Howells #define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */ 8196433f6eSDavid Howells 8296433f6eSDavid Howells /* 8396433f6eSDavid Howells * Convert the software IEEE trap enable and status bits into the 8496433f6eSDavid Howells * hardware fpcr format. 8596433f6eSDavid Howells * 8696433f6eSDavid Howells * Digital Unix engineers receive my thanks for not defining the 8796433f6eSDavid Howells * software bits identical to the hardware bits. The chip designers 8896433f6eSDavid Howells * receive my thanks for making all the not-implemented fpcr bits 8996433f6eSDavid Howells * RAZ forcing us to use system calls to read/write this value. 9096433f6eSDavid Howells */ 9196433f6eSDavid Howells 9296433f6eSDavid Howells static inline unsigned long ieee_swcr_to_fpcr(unsigned long sw)9396433f6eSDavid Howellsieee_swcr_to_fpcr(unsigned long sw) 9496433f6eSDavid Howells { 9596433f6eSDavid Howells unsigned long fp; 9696433f6eSDavid Howells fp = (sw & IEEE_STATUS_MASK) << 35; 9796433f6eSDavid Howells fp |= (sw & IEEE_MAP_DMZ) << 36; 9896433f6eSDavid Howells fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0); 9996433f6eSDavid Howells fp |= (~sw & (IEEE_TRAP_ENABLE_INV 10096433f6eSDavid Howells | IEEE_TRAP_ENABLE_DZE 10196433f6eSDavid Howells | IEEE_TRAP_ENABLE_OVF)) << 48; 10296433f6eSDavid Howells fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57; 10396433f6eSDavid Howells fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); 10496433f6eSDavid Howells fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41; 10596433f6eSDavid Howells return fp; 10696433f6eSDavid Howells } 10796433f6eSDavid Howells 10896433f6eSDavid Howells static inline unsigned long ieee_fpcr_to_swcr(unsigned long fp)10996433f6eSDavid Howellsieee_fpcr_to_swcr(unsigned long fp) 11096433f6eSDavid Howells { 11196433f6eSDavid Howells unsigned long sw; 11296433f6eSDavid Howells sw = (fp >> 35) & IEEE_STATUS_MASK; 11396433f6eSDavid Howells sw |= (fp >> 36) & IEEE_MAP_DMZ; 11496433f6eSDavid Howells sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV 11596433f6eSDavid Howells | IEEE_TRAP_ENABLE_DZE 11696433f6eSDavid Howells | IEEE_TRAP_ENABLE_OVF); 11796433f6eSDavid Howells sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE); 11896433f6eSDavid Howells sw |= (fp >> 47) & IEEE_MAP_UMZ; 11996433f6eSDavid Howells sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO; 12096433f6eSDavid Howells return sw; 12196433f6eSDavid Howells } 12296433f6eSDavid Howells 12396433f6eSDavid Howells 12496433f6eSDavid Howells #endif /* _UAPI__ASM_ALPHA_FPU_H */ 125