40 #include <asm/cpu-features.h>
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
68 /* SW interrupts 0,1 are used for interprocessor signaling */
95 		 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other  in bmips_smp_setup()
113 		/* enable raceless SW interrupts */  in bmips_smp_setup()
122 		/* clear any pending SW interrupts */  in bmips_smp_setup()
162  * IPI IRQ setup - runs on CPU0
189  * Tell the hardware to boot CPUx - runs on CPU0
199 	 *   bmips_reset_nmi_vec @ a000_0000 ->  in bmips_boot_secondary()
200 	 *   bmips_smp_entry ->  in bmips_boot_secondary()
201 	 *   plat_wired_tlb_setup (cached function call; optional) ->  in bmips_boot_secondary()
205 	 *   play_dead WAIT loop ->  in bmips_boot_secondary()
206 	 *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->  in bmips_boot_secondary()
207 	 *   eret to play_dead ->  in bmips_boot_secondary()
208 	 *   bmips_secondary_reentry ->  in bmips_boot_secondary()
248  * Early setup - runs on secondary CPU after cache probe
267  * Late setup - runs on secondary CPU before entering the idle loop
284  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
296 	int action = irq - IPI0_IRQ;  in bmips5000_ipi_interrupt()
320  * We use one inbound SW IRQ for each CPU.
344 	int action, cpu = irq - IPI0_IRQ;  in bmips43xx_ipi_interrupt()
412 	 * wait for SW interrupt from bmips_boot_secondary(), then jump  in play_dead()
469 	memcpy((void *)dst, start, end - start);  in bmips_wr_vec()
470 	dma_cache_wback(dst, end - start);  in bmips_wr_vec()
471 	local_flush_icache_range(dst, dst + (end - start));  in bmips_wr_vec()
491 	int shift = info->cpu & 0x01 ? 16 : 0;  in bmips_set_reset_vec_remote()
492 	u32 mask = ~(0xffff << shift), val = info->val >> 16;  in bmips_set_reset_vec_remote()
499 		if (info->cpu & 0x02) {  in bmips_set_reset_vec_remote()
550 		 *  - CPU1 will run this from uncached space  in bmips_ebase_setup()
551 		 *  - None of the cacheflush functions are set up yet  in bmips_ebase_setup()
553 		set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,  in bmips_ebase_setup()
601 		set_c0_brcm_bus_pll(BIT(22));  in bmips_cpu_setup()
605 		clear_c0_brcm_bus_pll(BIT(22));  in bmips_cpu_setup()
607 		/* clear BHTD to enable branch history table */  in bmips_cpu_setup()
608 		clear_c0_brcm_reset(BIT(16));  in bmips_cpu_setup()
610 		/* Flush and enable RAC */  in bmips_cpu_setup()
630 		/* Enable data RAC */  in bmips_cpu_setup()
653 		/* clear BHTD to enable branch history table */  in bmips_cpu_setup()
654 		clear_c0_brcm_config_0(BIT(21));  in bmips_cpu_setup()
656 		/* XI/ROTR enable */  in bmips_cpu_setup()
657 		set_c0_brcm_config_0(BIT(23));  in bmips_cpu_setup()
658 		set_c0_brcm_cmt_ctrl(BIT(15));  in bmips_cpu_setup()
662 		/* enable RDHWR, BRDHWR */  in bmips_cpu_setup()
663 		set_c0_brcm_config(BIT(17) | BIT(21));  in bmips_cpu_setup()
680 		/* XI enable */  in bmips_cpu_setup()
681 		set_c0_brcm_config(BIT(27));  in bmips_cpu_setup()
683 		/* enable MIPS32R2 ROR instruction for XI TLB handlers */  in bmips_cpu_setup()