Lines Matching +full:sw +full:- +full:enable +full:- +full:bit
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
172 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
175 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
178 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
227 …USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change …
228 …USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the …
244 …USHORT ASIC_Init; //Function Table, used by various SW components,lat…
246 …USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW comp…
249 …USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW comp…
250 …USHORT EnableCRTCMemReq; //Function Table,directly used by various SW compon…
251 …USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,cal…
252 …USHORT DVOEncoderControl; //Function Table,directly used by various SW compon…
254 …USHORT SetEngineClock; //Function Table,directly used by various SW compon…
255 …USHORT SetMemoryClock; //Function Table,directly used by various SW compon…
256 …USHORT SetPixelClock; //Function Table,directly used by various SW compon…
257 …USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW comp…
258 …USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW comp…
259 …USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW comp…
261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
262 …USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW comp…
265 …USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW compon…
266 …USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW componen…
267 …USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW compon…
268 …USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW compon…
269 …USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW compon…
270 …USHORT DVOOutputControl; //Atomic Table, directly used by various SW compon…
273 …USHORT TVEncoderControl; //Function Table,directly used by various SW compon…
278 …USHORT BlankCRTC; //Atomic Table, directly used by various SW compon…
279 …USHORT EnableCRTC; //Atomic Table, directly used by various SW compon…
280 …USHORT GetPixelClock; //Atomic Table, directly used by various SW compon…
281 …USHORT EnableVGA_Render; //Function Table,directly used by various SW compon…
283 …USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW compon…
284 …USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,late…
286 …USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW compon…
291 …USHORT GetMemoryClock; //Atomic Table, directly used by various SW compon…
292 …USHORT GetEngineClock; //Atomic Table, directly used by various SW compon…
293 …USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW compon…
294 …USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW compon…
295 …USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW compon…
299 …USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW comp…
300 …USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW comp…
301 …USHORT SpeedFanControl; //Function Table,indirectly used by various SW comp…
302 …USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW compon…
303 …USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW comp…
304 …USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW comp…
305 …USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW comp…
307 …USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW comp…
309 …USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW compon…
310 …USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW compon…
311 … //Function Table,directly and/or indirectly used by various SW components,latest ve…
312 …USHORT DAC1OutputControl; //Atomic Table, directly used by various SW compon…
313 …USHORT DAC2OutputControl; //Atomic Table, directly used by various SW compon…
315 …USHORT ClockSource; //Atomic Table, indirectly used by various SW comp…
316 …USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW comp…
317 …USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW comp…
318 …USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW componen…
319 …USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW componen…
320 …USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW componen…
321 …USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW component…
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
427 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
677 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
709 UCHAR ucLaneNum; // how many lanes to enable
730 …ne ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
732 // ATOM_ENABLE: Enable Encoder
778 UCHAR ucLaneNum; // how many lanes to enable
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
860 UCHAR ucLaneNum; // how many lanes to enable
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
919 UCHAR ucLaneNum; // how many lanes to enable
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
953 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1081 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1120 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1215 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1371 …UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT …
1573 …o; // Different bits for different purpose, bit [7:4] as device index, bit[0]=For…
1622 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1624 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1625 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1650 // bit[1]= when VGA timing is used.
1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1652 // bit[4]= RefClock source for PPLL.
1654 // =1: other external clock source, which is pre-defined
1656 // bit[7:5]: reserved.
1657 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1698 // bit[1]= when VGA timing is used.
1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1700 // bit[4]= RefClock source for PPLL.
1702 …// =1: other external clock source, which is pre-defined …
1704 // bit[7:5]: reserved.
1705 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1748 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1802 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1940 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
1965 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2018 UCHAR ucMisc; // bit0=0: Enable single link
2019 // =1: Enable dual link
2043 // =1: Enable truncate
2047 // =1: Enable spatial dithering
2051 // =1: Enable temporal dithering
2088 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2089 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2148 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2149 // bit1=0: non-coherent mode
2353 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2355 …USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was…
2357 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2359 …USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will…
2360 …USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will…
2361 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2363 …USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will…
2364 …USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new …
2367 …USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, use…
2368 …USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2370 …USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, onl…
2371 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2379 USHORT IntegratedSystemInfo; // Shared by various SW components
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2381 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2382 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2436 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2437 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2438 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2443 …Y_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disa…
2444 …E_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disa…
2452 …EMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss c…
2453 …NGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss c…
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2762 …ityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2763 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2765 …RT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bi…
2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2799 … PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise se…
2812 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data…
2813 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW c…
2815 SW components can access the IGP system infor structure in the same way as before
2856 …ans FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver wi…
2870 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2871 Bit[3]=1: Only one power state(Performance) will be supported.
2873 Bit[4]=1: CLMC is supported and enabled on current system.
2875 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
2877 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v…
2879 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
2880 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2881 Bit[8]=1: CDLF is supported and enabled on current system.
2883 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2886 …: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 … - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit …
2896 …opulated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has t…
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2914 ucDockingPinBit: which bit in this register to read the pin status;
2925 …GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYST…
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3008 …UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal C…
3009 …UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status R…
3041 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3175 // = 0, [6:0]=SW assisted I2C ID
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3469 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3472 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3476 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3477 //Bit 6 5 4
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3512 … // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3523 // Bit7-3: Reserved
3559 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3560 //Bit 6 5 4
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3578 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3581 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 …_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW in…
3587 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3812 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3825 // note2: From RV770, the memory is more than 32bit addressable, so we will change
3834 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3838 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3840 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3884 //ucGPIO_ID pre-define id for multiple usage
3885 …SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
3887 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
3917 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
3940 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
3942 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
3944 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3945 …_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the …
3946 …_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the …
3966 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3983 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4091 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: fro…
4092 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4093 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4094 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4111 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
4112 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4113 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4114 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4132 USHORT usDeviceTag; //A bit vector to show what devices are supported
4133 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4143 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4243 …UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external …
4287 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4329 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
4340 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4341 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4345 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4346 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4479 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4572 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4573 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4574 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4575 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4577 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4578 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4665 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse i…
4745 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4785 …FO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
4863 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4879 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4881 bit[3]=0: Enable HW AUX mode detection logic
4885 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4886 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
4888 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4889 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4891 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4894 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4897 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4901 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4903 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4906 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4908 Bit[1]=0: DDR-DLL shut-down feature disabled.
4909 1: DDR-DLL shut-down feature enabled.
4910 Bit[2]=0: DDR-PLL Power down feature disabled.
4911 … 1: DDR-PLL Power down feature enabled.
4917 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
4930 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4931 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4943 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
4945 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4946 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5078 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5092 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b )…
5094 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5096 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5098 bit[3]=0: VBIOS fast boot is disable
5099 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
5100 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5102 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
5104 bit[3]=0: Enable AUX HW mode detection logic
5109 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5110 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
5112 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5113 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5115 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5118 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5121 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5125 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5127 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
5130 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
5132 Bit[1]=0: DDR-DLL shut-down feature disabled.
5133 1: DDR-DLL shut-down feature enabled.
5134 Bit[2]=0: DDR-PLL Power down feature disabled.
5135 … 1: DDR-PLL Power down feature enabled.
5143 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
5156 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5157 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5169 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5171 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5172 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5174 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5177 …equence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE …
5178 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5180 …sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable …
5181 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5184 …s: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off …
5185 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5188 …e time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable …
5189 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5279 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5295 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
5297 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5299 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5301 bit[3]=0: VBIOS fast boot is disable
5302 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
5304 ulGPUCapInfo: bit[0~2]= Reserved
5305 bit[3]=0: Enable AUX HW mode detection logic
5307 bit[4]=0: Disable DFS bypass feature
5308 =1: Enable DFS bypass feature
5310 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5311 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
5313 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5314 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5316 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5319 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5322 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5326 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to en…
5327 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
5330 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
5332 Bit[1]=0: DDR-DLL shut-down feature disabled.
5333 1: DDR-DLL shut-down feature enabled.
5334 Bit[2]=0: DDR-PLL Power down feature disabled.
5335 1: DDR-PLL Power down feature enabled.
5336 Bit[3]=0: GNB DPM is disabled
5341 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
5356 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5374 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5376 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5377 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5379 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5383 …equence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE …
5384 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5387 …sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable …
5388 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5391 …LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCD…
5392 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5395 …e time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable …
5396 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5413 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to p…
5415 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5416 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5417 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5418 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5438 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5441 …s; //Indicates how many bytes SW needs to write to th…
5446 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C pro…
5449 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
5479 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a cloc…
5600 … // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
5820 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
5821 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for…
5823 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_IN…
5824 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_IN…
5980 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5982 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5983 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5987 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5988 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6019 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
6020 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
6368 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6405 …nelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of…
6406 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6407 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6415 …ULONG ulFlags; // To enable/disable functionalities based on memory ty…
6424 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6432 …nelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of…
6433 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6434 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6556 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6563 …UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extende…
6580 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
6581 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6583 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6602 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6604 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6606 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6607 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6612 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6644 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6646 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6648 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6649 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6654 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6663 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6675 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6677 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6679 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6680 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6685 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6694 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6704 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
6713 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6715 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6724 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6741 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6757 …p; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ..…
6783 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
6815 /****************************SW I2C CNTL DEFINITIONS**********************/
6929 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
6931 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
6933 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
6935 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
6940 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6941 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6948 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
6950 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
6952 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
6954 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
7298 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7299 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7300 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7307 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7308 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7309 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7431 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7436 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7441 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7449 // [7:4] - connector type
7450 // = 1 - VGA connector
7451 // = 2 - DVI-I
7452 // = 3 - DVI-D
7453 // = 4 - DVI-A
7454 // = 5 - SVIDEO
7455 // = 6 - COMPOSITE
7456 // = 7 - LVDS
7457 // = 8 - DIGITAL LINK
7458 // = 9 - SCART
7459 // = 0xA - HDMI_type A
7460 // = 0xB - HDMI_type B
7461 // = 0xE - Special case1 (DVI+DIN)
7463 // [3:0] - DAC Associated
7464 // = 0 - no DAC
7465 // = 1 - DACA
7466 // = 2 - DACB
7467 // = 3 - External DAC
7532 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7598 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
7626 … 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a…
7642 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7652 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7662 …M_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, the…
7767 // Following definitions are for compatibility issue in different SW components.