Lines Matching +full:sw +full:- +full:enable +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
60 (div)->u.s.frac_width > 0)
62 #define selector_exists(sel) ((sel)->width != 0)
65 #define policy_lvm_en_exists(enable) ((enable)->offset != 0) argument
66 #define policy_ctl_exists(control) ((control)->offset != 0)
78 * based on the CCU policy in effect. One bit in each policy mask
86 u32 bit; /* bit used in all mask registers */ member
94 .bit = (_bit), \
98 * Gating control and status is managed by a 32-bit gate register.
101 * - (no gate)
103 * - hardware-only gating (auto-gating)
107 * of auto-gated clocks can be read from the gate status bit.
108 * - software-only gating
109 * Auto-gating is not available for this type of clock.
111 * clearing the enable bit. The current gate status of a gate
112 * under software control can be read from the gate status bit.
114 * status bit can be polled to verify that the gate has entered
116 * - selectable hardware or software gating
119 * determined by the hw_sw_sel bit of the gate register.
124 u32 en_bit; /* 0: disable; 1: enable */
131 * HW means this gate can be auto-gated
132 * SW means the state of this gate can be software controlled
135 * ENABLED means this software-managed gate is *supposed* to be enabled
138 #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
141 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
157 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
169 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
173 /* A hardware-or-enabled gate (enabled if not under hardware control) */
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
184 /* A software-only gate */
190 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
194 /* A hardware-only gate */
205 u32 en_bit; /* bit used to enable hysteresis */
221 * variable. If there are two dividers, they are the "pre-divider"
223 * there is no pre-divider.
225 * A fixed divider is any non-zero (positive) value, and it
228 * The value of a variable divider is maintained in a sub-field of a
229 * 32-bit divider register. The position of the field in the
235 * bits comprise the low-order portion of the divider field, and can
238 * fractional bits. Variable dividers with non-zero fraction width
240 * added 1 does *not* affect the low-order bit in this case, it
247 * been left-shifted by the fractional width of a divider. Dividing
268 u32 fixed; /* non-zero fixed divider value */
276 * FIXED means it is a fixed-rate divider
279 #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
283 /* A fixed (non-zero) divider */
315 * sub-field of a 32-bit selector register. The range of
353 * bit within a register. To signal a change, a 1 is written into
354 * that bit. To determine when the change has been completed, that
355 * trigger bit is polled; the read value will be 1 while the change
359 * case, the "pre-trigger" will be used when changing a clock's
360 * selector and/or its pre-divider.
364 u32 bit; /* trigger bit */ member
378 .bit = (_bit), \
423 * CCU policy control. To enable software update of the policy
425 * software update enable bit (LVM_EN). After an update the engine
426 * is restarted using the GO bit and either the GO_ATL or GO_AC bit.
430 u32 bit; /* POLICY_CONFIG_EN bit in register */ member
433 /* Policy enable initialization macro */
437 .bit = (_bit), \
457 struct bcm_lvm_en enable; member