1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ST Microelectronics SPEAr SPI CS GPIO Controller 8 9maintainers: 10 - Viresh Kumar <vireshk@kernel.org> 11 12description: > 13 SPEAr platform provides a provision to control chipselects of ARM PL022 Prime 14 Cell spi controller through its system registers, which otherwise remains 15 under PL022 control. If chipselect remain under PL022 control then they would 16 be released as soon as transfer is over and TxFIFO becomes empty. This is not 17 desired by some of the device protocols above spi which expect (multiple) 18 transfers without releasing their chipselects. 19 20 Chipselects can be controlled by software by turning them as GPIOs. SPEAr 21 provides another interface through system registers through which software can 22 directly control each PL022 chipselect. Hence, it is natural for SPEAr to 23 export the control of this interface as gpio. 24 25properties: 26 compatible: 27 const: st,spear-spics-gpio 28 29 reg: 30 maxItems: 1 31 32 gpio-controller: true 33 34 '#gpio-cells': 35 const: 2 36 37 st-spics,peripcfg-reg: 38 description: Offset of the peripcfg register. 39 $ref: /schemas/types.yaml#/definitions/uint32 40 41 st-spics,sw-enable-bit: 42 description: Bit offset to enable software chipselect control. 43 $ref: /schemas/types.yaml#/definitions/uint32 44 45 st-spics,cs-value-bit: 46 description: Bit offset to drive chipselect low or high. 47 $ref: /schemas/types.yaml#/definitions/uint32 48 49 st-spics,cs-enable-mask: 50 description: Bitmask selecting which chipselects to enable. 51 $ref: /schemas/types.yaml#/definitions/uint32 52 53 st-spics,cs-enable-shift: 54 description: Bit shift for programming chipselect number. 55 $ref: /schemas/types.yaml#/definitions/uint32 56 57required: 58 - compatible 59 - reg 60 - gpio-controller 61 - '#gpio-cells' 62 - st-spics,peripcfg-reg 63 - st-spics,sw-enable-bit 64 - st-spics,cs-value-bit 65 - st-spics,cs-enable-mask 66 - st-spics,cs-enable-shift 67 68additionalProperties: false 69 70examples: 71 - | 72 gpio@e0700000 { 73 compatible = "st,spear-spics-gpio"; 74 reg = <0xe0700000 0x1000>; 75 st-spics,peripcfg-reg = <0x3b0>; 76 st-spics,sw-enable-bit = <12>; 77 st-spics,cs-value-bit = <11>; 78 st-spics,cs-enable-mask = <3>; 79 st-spics,cs-enable-shift = <8>; 80 gpio-controller; 81 #gpio-cells = <2>; 82 }; 83