Lines Matching +full:sw +full:- +full:enable +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
20 #define IPROC_CLK_AON BIT(0)
23 #define IPROC_CLK_PLL_ASIU BIT(1)
26 #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
33 #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
36  * Some PLLs require the PLL SW override bit to be set before changes can be
39 #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
42  * Some PLLs use a different way to control clock power, via the PWRDWN bit in
45 #define IPROC_CLK_EMBED_PWRCTRL BIT(5)
51 #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
58 #define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
66 #define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
71 #define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
76 #define IPROC_CLK_PLL_CALC_PARAM BIT(10)
140  * To enable SW control of the PLL
186 	struct iproc_clk_enable_ctrl enable;  member