Lines Matching +full:sw +full:- +full:enable +full:- +full:bit
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
179 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
182 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
185 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
235 …USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change t…
236 …USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the …
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
258 …USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change t…
259 …USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the …
273 …USHORT ASIC_Init; //Function Table, used by various SW components,lat…
275 …USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW comp…
278 …USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW comp…
279 …USHORT EnableCRTCMemReq; //Function Table,directly used by various SW compon…
280 …USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW comp…
281 …USHORT DVOEncoderControl; //Function Table,directly used by various SW compon…
283 …USHORT SetEngineClock; //Function Table,directly used by various SW compon…
284 …USHORT SetMemoryClock; //Function Table,directly used by various SW compon…
285 …USHORT SetPixelClock; //Function Table,directly used by various SW compon…
286 …USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW comp…
287 …USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW comp…
288 …USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW comp…
290 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
291 …USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW comp…
294 …USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW compon…
295 …USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW componen…
296 …USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW compon…
297 …USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW compon…
298 …USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW compon…
299 …USHORT DVOOutputControl; //Atomic Table, directly used by various SW compon…
302 …USHORT SMC_Init; //Function Table,directly used by various SW compon…
307 …USHORT BlankCRTC; //Atomic Table, directly used by various SW compon…
308 …USHORT EnableCRTC; //Atomic Table, directly used by various SW compon…
309 …USHORT GetPixelClock; //Atomic Table, directly used by various SW compon…
310 …USHORT EnableVGA_Render; //Function Table,directly used by various SW compon…
312 …USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW compon…
313 …USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,late…
315 …USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW compon…
320 …USHORT GetMemoryClock; //Atomic Table, directly used by various SW compon…
321 …USHORT GetEngineClock; //Atomic Table, directly used by various SW compon…
322 …USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW compon…
323 …USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW compon…
324 …USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW compon…
328 …USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW comp…
329 …USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW comp…
330 …USHORT SpeedFanControl; //Function Table,indirectly used by various SW comp…
331 …USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW compon…
332 …USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW comp…
333 …USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW comp…
334 …USHORT Gfx_Init; //Atomic Table, indirectly used by various SW comp…
336 …USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW comp…
338 …USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW compon…
339 …USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW compon…
340 … //Function Table,directly and/or indirectly used by various SW components,latest ve…
341 …USHORT DAC1OutputControl; //Atomic Table, directly used by various SW compon…
342 …USHORT ReadEfuseValue; //Atomic Table, directly used by various SW compon…
344 …USHORT ClockSource; //Atomic Table, indirectly used by various SW comp…
345 …USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW comp…
346 …USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW comp…
347 …USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW componen…
348 …USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW componen…
349 …USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW componen…
350 …USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW componen…
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
457 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit […
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
589 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable
590 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable
593 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
813 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
845 UCHAR ucLaneNum; // how many lanes to enable
866 …NFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
868 // ATOM_ENABLE: Enable Encoder
915 UCHAR ucLaneNum; // how many lanes to enable
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1003 UCHAR ucLaneNum; // how many lanes to enable
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1062 UCHAR ucLaneNum; // how many lanes to enable
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1159 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1287 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1326 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1379 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1381 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1385 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1421 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1620 …UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT …
1848 …o; // Different bits for different purpose, bit [7:4] as device index, bit[0]=For…
1897 …UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1899 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1926 // bit[1]= when VGA timing is used.
1927 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1928 // bit[4]= RefClock source for PPLL.
1930 // =1: other external clock source, which is pre-defined
1932 // bit[7:5]: reserved.
1933 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1973 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1974 // bit[1]= when VGA timing is used.
1975 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1976 // bit[4]= RefClock source for PPLL.
1978 // =1: other external clock source, which is pre-defined
1980 // bit[7:5]: reserved.
1981 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
2023 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
2024 …// bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is p…
2025 // bit[5:4]= RefClock source for PPLL.
2030 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO:…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2056 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2057 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2058 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2079 …UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucD…
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATI…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2121 …cDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2175 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2279 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2313 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2338 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2403 UCHAR ucMisc; // bit0=0: Enable single link
2404 // =1: Enable dual link
2427 // =1: Enable truncate
2431 // =1: Enable spatial dithering
2435 // =1: Enable temporal dithering
2473 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2474 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2531 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2532 // bit1=0: non-coherent mode
2789 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2791 …USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was…
2793 USHORT SMU_Info; // Shared by various SW components,latest version 1.1
2795 …USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will…
2796 …USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will…
2797 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2799 …USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will…
2800 …USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new …
2803 …USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, use…
2804 …USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2806 …USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, onl…
2807 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2815 USHORT IntegratedSystemInfo; // Shared by various SW components
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2817 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2818 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2877 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2878 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2879 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2884 …OCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disa…
2885 …OCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disa…
2893 …Y_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss c…
2894 …E_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss c…
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3139 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3140 UCHAR ucReserved:2; // Bit[3:2] Reserved
3141 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3178 … ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: …
3215 …lag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
3216 … //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3218 … usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bi…
3227 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3252 … PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise se…
3265 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data…
3266 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW c…
3268 SW components can access the IGP system infor structure in the same way as before
3309 …ans FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver wi…
3323 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3324 Bit[3]=1: Only one power state(Performance) will be supported.
3326 Bit[4]=1: CLMC is supported and enabled on current system.
3328 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
3330 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v…
3332 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
3333 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
3334 Bit[8]=1: CDLF is supported and enabled on current system.
3336 Bit[9]=1: DLL Shut Down feature is enabled on current system.
3339 …: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 … - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit …
3349 …opulated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has t…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3367 ucDockingPinBit: which bit in this register to read the pin status;
3378 …GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYST…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3462 …UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal C…
3463 …UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status R…
3517 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3652 // = 0, [6:0]=SW assisted I2C ID
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3949 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3952 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3956 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3957 //Bit 6 5 4
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4003 … // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
4014 // Bit7-3: Reserved
4050 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
4051 //Bit 6 5 4
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4069 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
4072 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 …_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW in…
4078 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4294 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
4308 // note2: From RV770, the memory is more than 32bit addressable, so we will change
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4372 …SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
4374 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4410 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
4433 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
4435 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
4437 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
4438 …_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the …
4439 …_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the …
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4584 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: fro…
4585 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4586 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4587 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4604 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4606 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4607 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4625 USHORT usDeviceTag; //A bit vector to show what devices are supported
4626 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4636 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4744 … ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4830 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
4832 …R_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not.
4834 #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not.
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4845 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4849 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4865 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4866 …USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used st…
4867 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4868 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4871 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4872 …USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used st…
4873 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5181 // 14:7 - PSI0_VID
5182 // 6 - PSI0_EN
5183 // 5 - PSI1
5184 // 4:2 - load line slope trim.
5185 // 1:0 - offset trim,
5240 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xf…
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuse…
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuse…
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5514 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD
5519 …EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5684 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
5731 …FO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
5809 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5825 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5827 bit[3]=0: Enable HW AUX mode detection logic
5831 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5832 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
5834 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5835 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5837 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5843 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5847 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5849 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
5852 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5857 1: DDR-PLL Power down feature enabled.
5863 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
5876 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5889 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5891 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5892 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
6024 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
6029 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6043 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b…
6045 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6047 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6049 bit[3]=0: VBIOS fast boot is disable
6050 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
6051 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
6053 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6055 bit[3]=0: Enable AUX HW mode detection logic
6060 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6061 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
6063 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6064 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6066 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6072 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6076 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
6078 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6081 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6086 1: DDR-PLL Power down feature enabled.
6094 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
6107 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6120 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6122 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6123 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
6125 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6128 …equence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE …
6129 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6131 …sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable …
6132 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6135 …s: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off …
6136 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6139 …e time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable …
6140 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6231 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6247 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6249 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6251 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6253 bit[3]=0: VBIOS fast boot is disable
6254 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
6256 ulGPUCapInfo: bit[0~2]= Reserved
6257 bit[3]=0: Enable AUX HW mode detection logic
6259 bit[4]=0: Disable DFS bypass feature
6260 =1: Enable DFS bypass feature
6262 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6263 …Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective sin…
6265 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6266 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6268 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6274 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6278 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to en…
6279 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6282 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6287 1: DDR-PLL Power down feature enabled.
6288 Bit[3]=0: GNB DPM is disabled
6293 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is reques…
6308 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6326 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6328 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6329 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
6331 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6335 …equence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE …
6336 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6339 …sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable …
6340 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6343 …LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCD…
6344 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6347 …e time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable …
6348 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6365 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to p…
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6368 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6369 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6370 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6598 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
6601 …s; //Indicates how many bytes SW needs to write to th…
6606 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C pro…
6609 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
6639 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a cloc…
6761 … // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
6985 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
6986 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for…
6988 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_IN…
6989 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_IN…
7146 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7148 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7149 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7153 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7154 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7187 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
7188 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
7577 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7614 …nelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of…
7615 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7624 …ULONG ulFlags; // To enable/disable functionalities based on mem…
7633 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7641 …nelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of…
7642 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7769 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7776 …UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS …
7793 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7794 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7796 …UCHAR ucFlag; // To enable/disable functionalities based on memo…
7815 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7819 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7820 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7825 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7857 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7861 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7862 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7867 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7889 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7893 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7894 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7899 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7918 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7924 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7929 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7949 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7955 …ol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: …
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7990 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
8006 …p; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ..…
8061 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
8104 /****************************SW I2C CNTL DEFINITIONS**********************/
8218 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
8220 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
8222 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
8224 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8237 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
8239 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
8241 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
8243 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
8573 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8574 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8575 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8582 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8583 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8584 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8594 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8595 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8596 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8601 …fset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Lin…
8602 …t of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8603 … of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8604 …set of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Lin…
8605 …f PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8606 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8755 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8760 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8765 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8773 // [7:4] - connector type
8774 // = 1 - VGA connector
8775 // = 2 - DVI-I
8776 // = 3 - DVI-D
8777 // = 4 - DVI-A
8778 // = 5 - SVIDEO
8779 // = 6 - COMPOSITE
8780 // = 7 - LVDS
8781 // = 8 - DIGITAL LINK
8782 // = 9 - SCART
8783 // = 0xA - HDMI_type A
8784 // = 0xB - HDMI_type B
8785 // = 0xE - Special case1 (DVI+DIN)
8787 // [3:0] - DAC Associated
8788 // = 0 - no DAC
8789 // = 1 - DACA
8790 // = 2 - DACB
8791 // = 3 - External DAC
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8922 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
8950 … 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a…
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8976 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8986 …M_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, the…
9095 // Following definitions are for compatiblity issue in different SW components.
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )