| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | synopsys-dw-mshc-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
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| H A D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ul
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| /freebsd/crypto/openssl/ssl/quic/ |
| H A D | quic_ackm.c | 2 * Copyright 2022-2025 The OpenSSL Project Authors. All Rights Reserved.
46 * list non-monotonically, so packet numbers must be greater than or equal
49 uint64_t watermark; member
53 * to the list. This is usually one less than watermark, except when we have
64 return (unsigned long)pkt->pkt_num; in tx_pkt_info_hash()
70 if (a->pkt_num < b->pkt_num) in tx_pkt_info_compare()
71 return -1; in tx_pkt_info_compare()
72 if (a->pkt_num > b->pkt_num) in tx_pkt_info_compare()
80 ossl_list_tx_history_init(&h->packets); in tx_pkt_history_init()
81 h->watermark = 0; in tx_pkt_history_init()
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-pl022.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 -
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| /freebsd/crypto/openssl/include/internal/ |
| H A D | quic_fc.h | 2 * Copyright 2022-2024 The OpenSSL Project Authors. All Rights Reserved.
22 * For discussion, see doc/designs/quic-design/quic-fc.md.
27 QUIC_TXFC *parent; /* stream-level iff non-NULL */
33 * Initialises a TX flow controller. conn_txfc should be non-NULL and point to
34 * the connection-level flow controller if the TXFC is for stream-level flow
40 * Gets the parent (i.e., connection-level) TX flow controller. Returns NULL if
41 * called on a connection-level TX flow controller.
46 * Bump the credit watermark (CWM) value. This is the 'On TX Window Updated'
47 * operation. This function is a no-op if it has already been called with an
62 * If called on a stream-level TXFC, ossl_quic_txfc_get_credit is called on
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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| /freebsd/crypto/openssl/doc/designs/quic-design/ |
| H A D | quic-fc.md | 5 ---------------------------------
8 transmission of stream data could be prevented by connection-level flow control,
9 by stream-level flow control, or both. Flow control uses a credit-based model in
14 It is important to note that both connection and stream-level flow control
32 Connection-level flow control is controlled by the `MAX_DATA` frame;
33 stream-level flow control is controlled by the `MAX_STREAM_DATA` frame.
38 our connection-level credit, and a conformant QUIC implementation can choose to
43 Note that it follows from the above that the CRYPTO-frame stream is not subject
54 | |<-- credit| -->| |
55 | <-|- threshold -|----->| |
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| /freebsd/sys/riscv/sifive/ |
| H A D | sifive_uart.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
91 bas->regiowidth = 4; in sfuart_probe()
104 /* Enable RX and configure the watermark so that we get an interrupt in sfuart_init()
110 /* Enable TX and configure the watermark so that we get an interrupt in sfuart_init()
140 * we've configured the watermark to be 0 and that interrupts are off in sfuart_rxready()
141 * when using the low-level console function, and read the interrupt in sfuart_rxready()
172 error = sfuart_probe(&sc->sc_bas); in sfuart_bus_probe()
176 sc->sc_rxfifosz = SFUART_RX_FIFO_DEPTH; in sfuart_bus_probe()
177 sc->sc_txfifosz = SFUART_TX_FIFO_DEPTH; in sfuart_bus_probe()
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| H A D | sifive_spi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
84 #define SFSPI_LOCK(sc) mtx_lock(&(sc)->mtx)
85 #define SFSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
86 #define SFSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
87 #define SFSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
91 * From Sifive-Unleashed-FU540-C000-v1.0.pdf page 101.
102 #define SFSPI_REG_RXDATA 0x4C /* Rx FIFO data */
103 #define SFSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
104 #define SFSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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| /freebsd/sys/dev/usb/net/ |
| H A D | if_smscreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * it is Copyrighted (C) 2007-2008 SMSC.
42 * ---------------
43 * Tx frames are prefixed with an 8-byte header which describes the frame
46 * +------------+------------+--- . . . . . . . . . . . . ---+
48 * +------------+------------+--- . . . . . . . . . . . . ---+
75 * --------------
76 * Rx frames are prefixed with an 4-byte status header which describes any
80 * +------------+--- . . . . . . . . . . . . ---+
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| /freebsd/sys/dev/flash/ |
| H A D | cqspi.h | 1 /*-
2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
96 #define CQSPI_RXTHRESH 0x34 /* RX Threshold Register */
108 #define CQSPI_INDRDWATER 0x64 /* Indirect Read Transfer Watermark Register */
112 #define CQSPI_INDWRWATER 0x74 /* Indirect Write Transfer Watermark Register */
|
| /freebsd/sys/dev/mmc/host/ |
| H A D | dwmmc_reg.h | 1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
80 #define SDMMC_CMD_SEND_ASTOP (1 << 12) /* Send stop command at end of data tx/rx */
97 #define SDMMC_FIFOTH 0x4C /* FIFO Threshold Watermark Register */
99 #define SDMMC_FIFOTH_RXWMARK_S 16 /* FIFO threshold watermark level */
100 #define SDMMC_FIFOTH_TXWMARK_S 0 /* FIFO threshold watermark level */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
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| /freebsd/sys/dev/uart/ |
| H A D | uart_dev_msm.c | 1 /*-
50 bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
52 bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
57 * Low-level UART interface.
140 bas->regiowidth = 4; in msm_probe()
150 if (bas->rclk == 0) in msm_init()
151 bas->rclk = DEF_CLK; in msm_init()
153 KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk")); in msm_init()
168 * Configure Tx and Rx watermarks configuration registers. in msm_init()
169 * TX watermark value is set to 0 - interrupt is generated when in msm_init()
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| H A D | uart_dev_msm.h | 1 /*-
31 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
57 /* 8-N-1 Configuration */
82 /* UART DM TX FIFO Registers - 4, write only */
140 /* UART Transmit/Receive FIFO Watermark Register */
146 /* Interrupt generated when no of words in RX FIFO is greater than this value */
152 /* Used for RX transfer initialization */
154 /* Default DMRX value - any value bigger than FIFO size would be fine */
163 * Single-Character mode for RX channel (every character received
164 * is zero-padded into a word).
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| /freebsd/sys/dev/ae/ |
| H A D | if_aereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 #define AE_ISR_RXD_UPDATED 0x00020000 /* Rx status updated. */
84 #define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
85 #define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
89 * L2 supports 64-bit addressing but all rings base addresses
97 Should be 120-byte aligned (i.e.
99 have 128-byte alignment). */
100 #define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
101 Should be 4-byte aligned. */
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| /freebsd/sys/dev/cxgbe/firmware/ |
| H A D | t6fw_cfg_uwire.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t5fw_cfg_fpga.txt | 3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
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| H A D | t6fw_cfg_fpga.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t4fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
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| H A D | t5fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/dev/bnxt/bnxt_re/ |
| H A D | bnxt_re.h | 2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term
99 * min_not_zero - return the minimum that is _not_ zero, unless both are zero
165 ((rdev)->chip_ctx->hwrm_cmd_max_timeout * 1000)
184 #define BNXT_RE_MSIX_FROM_MOD_PARAM -1
390 spin_lock(&(_rdev)->res_list[_type].lock); \
391 list_add_tail(&(_res)->dbr_list, \
392 &(_rdev)->res_list[_type].head); \
393 spin_unlock(&(_rdev)->res_list[_type].lock); \
398 spin_lock(&(_rdev)->res_list[_type].lock); \
399 list_del(&(_res)->dbr_list); \
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| /freebsd/sys/dev/thunderbolt/ |
| H A D | nhi_reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
42 #define GENMASK(h, l) (((~0U) >> (31 - (h))) ^ ((~0U) >> (31 - (l)) >> 1))
62 * TX and RX descriptors are packed together. There are only definitions
81 * One 32-bit status register encodes one status bit per ring indicates that
82 * the watermark from the control descriptor has been reached.
87 * TX and RX Tables. These are 32 byte control fields for each ring.
95 #define TX_TABLE_E2E (1 << 28) /* End-to-end flow control */
103 #define RX_TABLE_E2E (1 << 28) /* End-to-end flow control */
113 * Interrupt status for RX, TX, and Nearly Empty events, one bit per
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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| /freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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