1 /*-
50     bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
52     bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
57  * Low-level UART interface.
140 	bas->regiowidth = 4;  in msm_probe()
150 	if (bas->rclk == 0)  in msm_init()
151 		bas->rclk = DEF_CLK;  in msm_init()
153 	KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));  in msm_init()
168 	 * Configure Tx and Rx watermarks configuration registers.  in msm_init()
169 	 * TX watermark value is set to 0 - interrupt is generated when  in msm_init()
174 	/* Set RX watermark value */  in msm_init()
200 	/* Enable/Disable Rx/Tx DM interfaces */  in msm_init()
235 		    && --limit)  in msm_putc()
284  * High-level UART interface.
325 	bas = &sc->sc_bas;  in msm_bus_probe()
326 	bas->regiowidth = 4;  in msm_bus_probe()
328 	sc->sc_txfifosz = 64;  in msm_bus_probe()
329 	sc->sc_rxfifosz = 64;  in msm_bus_probe()
331 	device_set_desc(sc->sc_dev, "Qualcomm HSUART");  in msm_bus_probe()
340 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_attach()
342 	sc->sc_hwiflow = 0;  in msm_bus_attach()
343 	sc->sc_hwoflow = 0;  in msm_bus_attach()
346 	u->ier = UART_DM_IMR_ENABLED;  in msm_bus_attach()
349 	uart_setreg(bas, UART_DM_IMR, u->ier);  in msm_bus_attach()
361 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_transmit()
364 	uart_lock(sc->sc_hwmtx);  in msm_bus_transmit()
367 	for (i = 0; i < sc->sc_txdatasz; i++) {  in msm_bus_transmit()
369 		msm_putc(bas, sc->sc_txbuf[i]);  in msm_bus_transmit()
374 	u->ier |= UART_DM_TX_READY;  in msm_bus_transmit()
375 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_transmit()
382 	sc->sc_txbusy = 1;  in msm_bus_transmit()
383 	uart_unlock(sc->sc_hwmtx);  in msm_bus_transmit()
402 	bas = &sc->sc_bas;  in msm_bus_receive()
403 	uart_lock(sc->sc_hwmtx);  in msm_bus_receive()
408 	u->ier |= UART_DM_RXLEV;  in msm_bus_receive()
409 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_receive()
415 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;  in msm_bus_receive()
419 		/* Read RX FIFO */  in msm_bus_receive()
426 	uart_unlock(sc->sc_hwmtx);  in msm_bus_receive()
437 	if (sc->sc_bas.rclk == 0)  in msm_bus_param()
438 		sc->sc_bas.rclk = DEF_CLK;  in msm_bus_param()
440 	KASSERT(sc->sc_bas.rclk != 0, ("msm_init: Invalid rclk"));  in msm_bus_param()
442 	uart_lock(sc->sc_hwmtx);  in msm_bus_param()
443 	error = msm_uart_param(&sc->sc_bas, baudrate, databits, stopbits,  in msm_bus_param()
445 	uart_unlock(sc->sc_hwmtx);  in msm_bus_param()
454 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ipend()
458 	uart_lock(sc->sc_hwmtx);  in msm_bus_ipend()
465 	/* Uart RX starting, notify upper layer */  in msm_bus_ipend()
467 		u->ier &= ~UART_DM_RXLEV;  in msm_bus_ipend()
468 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
473 	/* Stale RX interrupt */  in msm_bus_ipend()
488 		u->ier &= ~UART_DM_TX_READY;  in msm_bus_ipend()
489 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
492 		if (sc->sc_txbusy != 0)  in msm_bus_ipend()
498 		u->ier &= ~UART_DM_TXLEV;  in msm_bus_ipend()
499 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
502 		if (sc->sc_txbusy != 0)  in msm_bus_ipend()
506 	uart_unlock(sc->sc_hwmtx);  in msm_bus_ipend()
534 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_grab()
540 	uart_lock(sc->sc_hwmtx);  in msm_bus_grab()
544 	uart_unlock(sc->sc_hwmtx);  in msm_bus_grab()
551 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ungrab()
556 	uart_lock(sc->sc_hwmtx);  in msm_bus_ungrab()
557 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ungrab()
559 	uart_unlock(sc->sc_hwmtx);  in msm_bus_ungrab()
573 	{"qcom,msm-uartdm-v1.4",	(uintptr_t)&uart_msm_class},
574 	{"qcom,msm-uartdm",		(uintptr_t)&uart_msm_class},