Lines Matching +full:rx +full:- +full:watermark
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
36 - const: ciu
41 altr,sysmgr-syscon:
42 $ref: /schemas/types.yaml#/definitions/phandle-array
44 - items:
45 - description: phandle to the sysmgr node
46 - description: register offset that controls the SDMMC clock phase
47 - description: register shift for the smplsel(drive in) setting
50 that contains the SDMMC clock-phase control register. The first value is
56 - $ref: synopsys-dw-mshc-common.yaml#
58 - if:
62 const: altr,socfpga-dw-mshc
65 altr,sysmgr-syscon: true
69 altr,sysmgr-syscon: false
72 - compatible
73 - reg
74 - interrupts
75 - clocks
76 - clock-names
81 - |
83 compatible = "snps,dw-mshc";
87 clock-names = "biu", "ciu";
89 dma-names = "rx-tx";
91 reset-names = "reset";
92 vmmc-supply = <&buck8>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 broken-cd;
96 bus-width = <8>;
97 cap-mmc-highspeed;
98 cap-sd-highspeed;
99 card-detect-delay = <200>;
100 max-frequency = <200000000>;
101 clock-frequency = <400000000>;
102 data-addr = <0x200>;
103 fifo-depth = <0x80>;
104 fifo-watermark-aligned;