Lines Matching +full:rx +full:- +full:watermark
3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
34 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
41 # to allow for this. And because of the MSI-X resource allocation
44 # or we'll need to move the Unified PF into the PF4-7 range since those
49 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
67 # 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
68 # Virtual Machines to directly access T4 functionality via SR-IOV
69 # Virtual Functions and "PCI Device Passthrough" -- this is especially
131 # minus 128-entries for FL and HP
151 # to use for TP RX payload
154 # TP RX payload page size
157 # TP number of RX channels
176 # NMSIX = 1088 # available MSI-X Vectors
187 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
191 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
199 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
206 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
213 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
224 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
231 # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
261 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
266 # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
272 # associated with it. Thus, the MSI-X Vector allocations we give to the
275 # one of PF0-3.
278 # All of the below PCI-E parameters are actually stored in various *_init.txt
281 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
282 # ports 0-3.
284 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
286 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
289 # Additionally, since the UnifiedPF isn't one of the per-port Physical
290 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
291 # different PCI Device IDs which will allow Unified and Per-Port Drivers
295 # Note that the actual values used for the PCI-E Intelectual Property will be
313 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
320 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
321 # Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
423 # bg_mem: %-age of mem to use for port/buffer group
424 # lpbk_mem: %-age of port/bg mem to use for loopback
425 # hwm: high watermark; bytes available when starting to send pause
427 # lwm: low watermark; bytes remaining when sending 'unpause' frame
429 # dwm: minimum delta between high and low watermark (in units of 100
473 # MSI-X Vectors: 736